01916nam 2200337 450 99657496000331620231211115046.01-5044-6343-910.1109/IEEESTD.2020.9036129(CKB)5280000000208121(NjHacI)995280000000208121(EXLCZ)99528000000020812120231211d2020 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrier1838-2019 - IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits /Institute of Electrical and Electronics EngineersNew York, New York :IEEE,2020.1 online resource (73 pages)IEEE Std 1838 is a die-centric standard; it applies to a die that is intended to be part of a multi-die stack. This standard defines die-level features that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in both pre-packaging, post-packaging, and board-level situations. The primary focus of inter-die interconnect technology addressed by this standard is through-silicon vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding.Microwave transmission linesStandardsMicrowave transmission linesStandards.621.38132NjHacINjHaclDOCUMENT9965749600033161838-2019 - IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits2584729UNISA