01002nam0 2200289 450 00001702720081006145029.088-8091-109-020081006d1995----km-y0itay50------baitaITy-------001yyEsercizi di analisi macroeconomicaRoberto Cellini, Flavio Delbono, Vincenzo DenicolòBolognaCLUEB1995296 p.24 cmMateriali didattici della Collana di economia32001Materiali didattici della Collana di economiaMacroeconomiaEsercizi339.07620Macroeconomiae argomenti connessi. Prontuari ed eserciziCellini,Roberto438185Delbono,Flavio33408Denicolò,Vincenzo437310ITUNIPARTHENOPE20081005RICAUNIMARC000017027023/2747780NAVA22008Esercizi di analisi macroeconomica1128987UNIPARTHENOPE01148nam 2200337 450 99657467120331620231214024958.01-5044-7426-0(CKB)4100000011774093(NjHacI)994100000011774093(EXLCZ)99410000001177409320231214d2009 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrier1800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline /Institute of Electrical and Electronics Engineers[Place of publication not identified] :IEEE,2009.1 online resourceFinish hardwareHardware industryFinish hardware.Hardware industry.683NjHacINjHaclDOCUMENT9965746712033161800-2009 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline2581488UNISA