01524nam 2200325 450 99655996580331620231205191950.0979-88-557-0213-2(CKB)28534578600041(NjHacI)9928534578600041(EXLCZ)992853457860004120231205d2023 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrier62530-2-2023 - IEEE/IEC International Standard--SystemVerilogPart 2 Universal Verification Methodology Language Reference Manual /IEEENew York, USA :IEEE,2023.1 online resource (461 pages)The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.Verification (Logic)Verification (Logic)160NjHacINjHaclBOOK99655996580331662530-2-2023 - IEEE3590377UNISA