04955nam 22008775 450 99646602300331620230406040521.03-540-69338-610.1007/978-3-540-69338-3(CKB)1000000000490640(EBL)3061644(SSID)ssj0000318106(PQKBManifestationID)11245577(PQKBTitleCode)TC0000318106(PQKBWorkID)10312415(PQKB)11489153(DE-He213)978-3-540-69338-3(MiAaPQ)EBC3061644(MiAaPQ)EBC6283992(PPN)123726565(EXLCZ)99100000000049064020100301d2007 u| 0engur|n|---|||||txtccrHigh Performance Embedded Architectures and Compilers[electronic resource] Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings /edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer1st ed. 2007.Berlin, Heidelberg :Springer Berlin Heidelberg :Imprint: Springer,2007.1 online resource (297 p.)Theoretical Computer Science and General Issues,2512-2029 ;4367International conference proceedings.3-540-69337-8 Includes bibliographical references and index.Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints.Theoretical Computer Science and General Issues,2512-2029 ;4367Computer scienceComputer arithmetic and logic unitsMicroprocessorsComputer architectureComputer input-output equipmentLogic designComputer networksTheory of ComputationArithmetic and Logic StructuresProcessor ArchitecturesInput/Output and Data CommunicationsLogic DesignComputer Communication NetworksComputer science.Computer arithmetic and logic units.Microprocessors.Computer architecture.Computer input-output equipment.Logic design.Computer networks.Theory of Computation.Arithmetic and Logic Structures.Processor Architectures.Input/Output and Data Communications.Logic Design.Computer Communication Networks.004.22De Bosschere Koenedthttp://id.loc.gov/vocabulary/relators/edtKaeli Davidedthttp://id.loc.gov/vocabulary/relators/edtStenström Peredthttp://id.loc.gov/vocabulary/relators/edtWhalley Davidedthttp://id.loc.gov/vocabulary/relators/edtUngerer Theoedthttp://id.loc.gov/vocabulary/relators/edtMiAaPQMiAaPQMiAaPQBOOK996466023003316High Performance Embedded Architectures and Compilers772079UNISA