09997nam 22009255 450 99646599570331620230406054950.03-540-74442-810.1007/978-3-540-74442-9(CKB)1000000000490694(SSID)ssj0000318340(PQKBManifestationID)11266632(PQKBTitleCode)TC0000318340(PQKBWorkID)10310235(PQKB)10225325(DE-He213)978-3-540-74442-9(MiAaPQ)EBC3063424(MiAaPQ)EBC337392(MiAaPQ)EBC6699191(Au-PeEL)EBL337392(CaONFJC)MIL135360(OCoLC)808680889(Au-PeEL)EBL6699191(PPN)123164451(EXLCZ)99100000000049069420100301d2007 u| 0engurnn|008mamaatxtccrIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation[electronic resource] 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings /edited by Nadine Azemard, Lars Svensson1st ed. 2007.Berlin, Heidelberg :Springer Berlin Heidelberg :Imprint: Springer,2007.1 online resource (XIV, 586 p.) Theoretical Computer Science and General Issues,2512-2029 ;4644Includes index.3-540-74441-X Includes bibliographical references and index.Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters.th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.Theoretical Computer Science and General Issues,2512-2029 ;4644Logic designMicroprocessorsComputer architectureElectronic digital computers—EvaluationComputer arithmetic and logic unitsComputer storage devicesMemory management (Computer science)Electronic circuitsLogic DesignProcessor ArchitecturesSystem Performance and EvaluationArithmetic and Logic StructuresComputer Memory StructureElectronic Circuits and SystemsLogic design.Microprocessors.Computer architecture.Electronic digital computers—Evaluation.Computer arithmetic and logic units.Computer storage devices.Memory management (Computer science).Electronic circuits.Logic Design.Processor Architectures.System Performance and Evaluation.Arithmetic and Logic Structures.Computer Memory Structure.Electronic Circuits and Systems.621.395Azemard Nadine1963-Svensson Lars1960-MiAaPQMiAaPQMiAaPQBOOK996465995703316Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation772134UNISA05345nam 2200697 450 991083058330332120210208165743.01-118-12272-01-283-42502-597866134250271-118-12264-X1-118-12263-11-118-12270-4(CKB)2560000000079110(EBL)817332(SSID)ssj0000592311(PQKBManifestationID)11410428(PQKBTitleCode)TC0000592311(PQKBWorkID)10735832(PQKB)11397850(MiAaPQ)EBC817332(PPN)170251683(OCoLC)775437890(EXLCZ)99256000000007911020170704h20122012 uy 0engur|n|---|||||txtccrOptimal control /Frank L. Lewis, Draguna L. Vrabie, Vassilis L. Syrmos3rd ed.Hoboken, New Jersey :John Wiley & Sons, Inc.,2012.©20121 online resource (554 p.)Description based upon print version of record.0-470-63349-2 Includes bibliographical references and index.Optimal Control; Contents; Preface; 1 Static Optimization; 1.1 Optimization without Constraints; 1.2 Optimization with Equality Constraints; 1.3 Numerical Solution Methods Problems; Problems; 2 Optimal Control of Discrete-Time Systems; 2.1 Solution of the General Discrete-Time Optimization Problem; 2.2 Discrete-Time Linear Quadratic Regulator; 2.3 Digital Control of Continuous-Time Systems; 2.4 Steady-State Closed-Loop Control and Suboptimal Feedback; 2.5 Frequency-Domain Results; Problems; 3 Optimal Control of Continuous-Time Systems; 3.1 The Calculus of Variations3.2 Solution of the General Continuous-Time Optimization Problem3.3 Continuous-Time Linear Quadratic Regulator; 3.4 Steady-State Closed-Loop Control and Suboptimal Feedback; 3.5 Frequency-Domain Results; Problems; 4 The Tracking Problem and Other LQR Extensions; 4.1 The Tracking Problem; 4.2 Regulator with Function of Final State Fixed; 4.3 Second-Order Variations in the Performance Index; 4.4 The Discrete-Time Tracking Problem; 4.5 Discrete Regulator with Function of Final State Fixed; 4.6 Discrete Second-Order Variations in the Performance Index; Problems5 Final-Time-Free And Constrained Input Control5.1 Final-Time-Free Problems; 5.2 Constrained Input Problems; Problems; 6 Dynamic Programming; 6.1 Bellman's Principle of Optimality; 6.2 Discrete-Time Systems; 6.3 Continuous-Time Systems; Problems; 7 Optimal Control for Polynomial Systems; 7.1 Discrete Linear Quadratic Regulator; 7.2 Digital Control of Continuous-Time Systems; Problems; 8 Output Feedback and Structured Control; 8.1 Linear Quadratic Regulator with Output Feedback; 8.2 Tracking a Reference Input; 8.3 Tracking by Regulator Redesign; 8.4 Command-Generator Tracker8.5 Explicit Model-Following Design8.6 Output Feedback in Game Theory and Decentralized Control; Problems; 9 Robustness And Multivariable Frequency-Domain Techniques; 9.1 Introduction; 9.2 Multivariable Frequency-Domain Analysis; 9.3 Robust Output-Feedback Design; 9.4 Observers and the Kalman Filter; 9.5 LQG/Loop-Transfer Recovery; 9.6 H8 DESIGN; Problems; 10 Differential Games; 10.1 Optimal Control Derived Using Pontryagin's Minimum Principle and the Bellman Equation; 10.2 Two-player Zero-sum Games; 10.3 Application of Zero-sum Games to H8 Control; 10.4 Multiplayer Non-zero-sum Games11 Reinforcement Learning and Optimal Adaptive Control11.1 Reinforcement Learning; 11.2 Markov Decision Processes; 11.3 Policy Evaluation and Policy Improvement; 11.4 Temporal Difference Learning and Optimal Adaptive Control; 11.5 Optimal Adaptive Control for Discrete-time Systems; 11.6 Integral Reinforcement Learning for Optimal Adaptive Control of Continuous-time Systems; 11.7 Synchronous Optimal Adaptive Control for Continuous-time Systems; Appendix a Review of Matrix Algebra; A.1 Basic Definitions and Facts; A.2 Partitioned Matrices; A.3 Quadratic Forms and DefinitenessA.4 Matrix Calculus A new edition of the classic text on optimal control theory As a superb introductory text and an indispensable reference, this new edition of Optimal Control will serve the needs of both the professional engineer and the advanced student in mechanical, electrical, and aerospace engineering. Its coverage encompasses all the fundamental topics as well as the major changes that have occurred in recent years. An abundance of computer simulations using MATLAB and relevant Toolboxes is included to give the reader the actual experience of applying the theory to real-world situations. Major tControl theoryMathematical optimizationControl theory.Mathematical optimization.629.8/312629.8312Lewis Frank L.30830Vrabie Draguna L.Syrmos Vassilis L.MiAaPQMiAaPQMiAaPQBOOK9910830583303321Optimal control226641UNINA