04623oam 2200661 450 99646591070331620210803201641.03-540-49519-310.1007/3-540-49519-3(CKB)1000000000211021(SSID)ssj0000323227(PQKBManifestationID)11247940(PQKBTitleCode)TC0000323227(PQKBWorkID)10296278(PQKB)11493359(DE-He213)978-3-540-49519-2(MiAaPQ)EBC3073203(MiAaPQ)EBC6495042(PPN)155174320(EXLCZ)99100000000021102120210803d1998 uy 0engurnn|008mamaatxtccrFormal methods in computer-aided design second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings /Ganesh Gopalakrishnan, Phillip Windley (editors)1st ed. 1998.Berlin :Springer,[1998]©19981 online resource (X, 538 p.) Lecture notes in computer science ;1522Bibliographic Level Mode of Issuance: Monograph3-540-65191-8 Includes bibliographical references and index.Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker.Lecture notes in computer science ;1522.Digital integrated circuitsComputer-aided designCongressesComputer engineeringComputer-aided designCongressesIntegrated circuitsVerificationCongressesAutomatic theorem provingCongressesFormal methods (Computer science)CongressesDigital integrated circuitsComputer-aided designComputer engineeringComputer-aided designIntegrated circuitsVerificationAutomatic theorem provingFormal methods (Computer science)621.392Windley Phillip J.1958-Gopalakrishnan GaneshFMCAD '98MiAaPQMiAaPQUtOrBLWBOOK996465910703316Formal Methods in Computer-Aided Design1891319UNISA