06356nam 22007575 450 99646533720331620200701111742.03-540-46183-310.1007/3-540-51284-5(CKB)1000000000233401(SSID)ssj0000325542(PQKBManifestationID)11254102(PQKBTitleCode)TC0000325542(PQKBWorkID)10325425(PQKB)10461792(DE-He213)978-3-540-46183-8(PPN)155219790(EXLCZ)99100000000023340120121227d1989 u| 0engurnn|008mamaatxtccrPARLE '89 - Parallel Architectures and Languages Europe[electronic resource] Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 12-16, 1989; Proceedings /edited by Eddy Odijk, Martin Rem, Jean-Claude Syre1st ed. 1989.Berlin, Heidelberg :Springer Berlin Heidelberg :Imprint: Springer,1989.1 online resource (XIII, 479 p.) Lecture Notes in Computer Science,0302-9743 ;365Bibliographic Level Mode of Issuance: Monograph3-540-51284-5 The cache coherence protocol of the Data Diffusion Machine -- Universal mechanisms for concurrency -- Serial multiport memory multiprocessors -- Modeling and analysis of multiprocessor systems with priority and multiple resources allocation to the tasks -- Achieving low cost synchronization in a multiprocessor system -- The Synchronous Dataflow MAchine: Architecture and performance -- The lady programming environment for distributed operating systems -- A static scheduling system for a parallel machine (SM)2-II -- Distributed implementation of programmed graph reduction -- Parallel object-oriented descriptions of graph reduction machines -- MaRS, a combinator graph reduction multiprocessor -- High-performance parallel graph reduction -- An efficient distributed garbage collection algorithm -- Mark DURING sweep rather than mark THEN sweep -- Architecture of a communication network processor -- The feasibility of a general-purpose parallel computer using WSI -- A coarse grain parallel architecture for functional languages -- A Functional Programming environment supporting execution, partial execution and transformation -- The gene concept and its implementation for a dataflow schemed parallel computer -- Hybrid structure: A scheme for handling data structures in a data flow environment -- Implementation conditions for delay insensitive circuits -- POOL and DOOM a survey of esprit 415 subproject A, Philips research laboratories -- Multi-level simulator for VLSI on the parallel object-oriented machine -- Overview of a parallel reduction machine project II -- A parallel database accelerator -- IDEAL & K-LEAF implementation: a progress report -- The sto//mann data flow machine -- Partheo: A parallel inference machine ESPRIT 415 subproject F.Since the first PARLE conference, PARLE '87, attracted more than 300 participants, it was considered a useful and successful forum and encouraged the organization of this second issue known as PARLE '89. The initiative for these conferences was taken by project 415 of ESPRIT (the European Strategic Programme for Research and Development in Information Technology of the Commission of the European Communities). Their scope covers central themes in the area of parallel architectures and languages, including such topics as concurrent, object-oriented, logic and functional programming; MIMD, dataflow, inference and reduction machines; design and verification of parallel systems; VLSI, WSI and RISC architectures; performance evaluation, memory management, systolic arrays, applications and special purpose architectures. The five invited lectures present the state of the art and advanced developments in major research areas related to the topics of the conference. Of the more than 150 submitted papers, 45 were selected for presentation. Furthermore the program of PARLE '89 comprises presentations on the subprojects which together constitute ESPRIT project 415. Parallel architectures based on a variety of programming styles (object-oriented, logic, functional, dataflow) are represented in these overviews.Lecture Notes in Computer Science,0302-9743 ;365Architecture, ComputerMicroprocessorsComputer communication systemsSpecial purpose computersComputer system failuresComputer programmingComputer System Implementationhttps://scigraph.springernature.com/ontologies/product-market-codes/I13057Processor Architectureshttps://scigraph.springernature.com/ontologies/product-market-codes/I13014Computer Communication Networkshttps://scigraph.springernature.com/ontologies/product-market-codes/I13022Special Purpose and Application-Based Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/I13030System Performance and Evaluationhttps://scigraph.springernature.com/ontologies/product-market-codes/I13049Programming Techniqueshttps://scigraph.springernature.com/ontologies/product-market-codes/I14010Architecture, Computer.Microprocessors.Computer communication systems.Special purpose computers.Computer system failures.Computer programming.Computer System Implementation.Processor Architectures.Computer Communication Networks.Special Purpose and Application-Based Systems.System Performance and Evaluation.Programming Techniques.003.3Odijk Eddyedthttp://id.loc.gov/vocabulary/relators/edtRem Martinedthttp://id.loc.gov/vocabulary/relators/edtSyre Jean-Claudeedthttp://id.loc.gov/vocabulary/relators/edtBOOK996465337203316PARLE '89 - Parallel Architectures and Languages Europe2831533UNISA