01394nam 2200373 450 99628055520331620231020005623.00-7381-3502-X(CKB)1000000000035538(NjHacI)991000000000035538(EXLCZ)99100000000003553820231020d2002 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierIEEE Std 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis /Institute of Electrical and Electronics Engineers (IEEE)New York :Institute of Electrical and Electronics Engineers (IEEE),2002.1 online resource (vii, 100 pages)0-7381-3501-1 Standard syntax and semantics for Verilog HDL-based RTL synthesis are described in this standard.IEEE Std 1364.1-2002Verilog (Computer hardware description language) Verilog (Computer hardware description language)StandardsVerilog (Computer hardware description language) Verilog (Computer hardware description language)Standards.621.392NjHacINjHaclDOCUMENT996280555203316IEEE Std 1364.1-20023574292UNISA