01878oam 2200409zu 450 99621026000331620210807003607.0(CKB)111026746740844(SSID)ssj0000558187(PQKBManifestationID)12224933(PQKBTitleCode)TC0000558187(PQKBWorkID)10560533(PQKB)11785711(NjHacI)99111026746740844(EXLCZ)9911102674674084420160829d1995 uy engur|||||||||||txtccrDefect and Fault-Tolerance in VLSI Systems, 1995 Workshop[Place of publication not identified]IEEE Computer Society Press19951 online resource (320 pages)Bibliographic Level Mode of Issuance: Monograph0-8186-7107-6 An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright by Book News, Inc., Portland, OR.Fault-tolerant computingCongressesIntegrated circuitsVery large scale integrationDesign and constructionFault-tolerant computingIntegrated circuitsVery large scale integrationDesign and construction.004.2PQKBBOOK996210260003316Defect and Fault-Tolerance in VLSI Systems, 1995 Workshop2407799UNISA