01825oam 2200409zu 450 99620735080331620210806235822.01-5090-9191-2(CKB)1000000000278188(SSID)ssj0000454352(PQKBManifestationID)12175328(PQKBTitleCode)TC0000454352(PQKBWorkID)10397927(PQKB)10408376(NjHacI)991000000000278188(EXLCZ)99100000000027818820160829d2006 uy engur|||||||||||txtccr2006 1st International Symposium on Wireless Pervasive Computing[Place of publication not identified]I E E E20061 online resource (viii, 584 pages) illustrationsBibliographic Level Mode of Issuance: Monograph0-7803-9410-0 This paper presents a new trace-back memory structure for Viterbi decoders that reduces power consumption by 63% compared to the conventional RAM based design. Instead of the intensive read and write operations as required in RAM based designs, the new memory is based on an array of registers connected with trace-back signals that decode the output bits on the fly. The structure is used together with appropriate clock and power-aware control signals. Based on a 0.35 /spl mu/m CMOS implementation the trace-back back memory consumes energy of 182 pJ.Ubiquitous computingCongressesUbiquitous computing004Institute of Electrical and Electronics Engineers,PQKBPROCEEDING9962073508033162006 1st International Symposium on Wireless Pervasive Computing2521896UNISA