01245cam a2200277 i 4500991001737919707536030723s1999 it 001 0 ita d887814195Xb12189868-39ule_instDip.to Beni CulturaliitaitaengIaia, Cristiano.451572Simbolismo funerario e ideologia alle origini di una civiltà urbana :forme rituali nelle sepolture villanoviane a Tarquinia e Vulci, e nel loro entroterra /Cristiano Iaia.Firenze :All'insegna del Giglio,1999.156 p. :ill. ;29 cm.Grandi contesti e problemi della protostoria italiana ;3.Contiene bibliografia: pp. 149-156Sommario in inglese: pp. 141-148VillanovianiItaliaRiti funebriItaliaAntichità.b1218986802-04-1423-07-03991001737919707536LE001 H1 172 4°12001000067015le001B.C.A. n. 122 del 31/12/2003pE22.00-l- 00000.i1312100502-03-04Simbolismo funerario e ideologia alle origini di una civiltà urbana145842UNISALENTOle00123-07-03ma -itait 0105375nam 22006854a 450 991101879760332120200520144314.0978661027201397812802720111280272015978047029946304702994609780470865125047086512197804700141030470014105(CKB)111087027096454(EBL)163123(OCoLC)54996408(SSID)ssj0000220702(PQKBManifestationID)11201762(PQKBTitleCode)TC0000220702(PQKBWorkID)10144738(PQKB)10135896(MiAaPQ)EBC163123(Perlego)2765970(EXLCZ)9911108702709645420030306d2003 uy 0engur|n|---|||||txtccrPhase lock loops and frequency synthesis /Venceslav F. KroupaNew York J. Wiley20031 online resource (336 p.)Description based upon print version of record.9780470848661 0470848669 Includes bibliographical references and index.Phase Lock Loops and Frequency Synthesis; Contents; Preface; 1 Basic Equations of the PLLs; 1.1 Introduction; 1.2 Basic Equations of the PLLs; 1.3 Solution of the Basic PLL Equation in the Time Domain; 1.3.1 Solution in the Closed Form; 1.3.2 Linearized Solution; 1.4 Solution of Basic PLL Equations in the Frequency Domain; 1.5 Order and Type of PLLs; 1.5.1 Order of PLLs; 1.5.2 Type of PLLs; 1.5.3 Steady State Errors; 1.6 Block Diagram Algebra; References; 2 PLLs of the First and Second Order; 2.1 PLLs of the First Order; 2.2 PLLs of the Second Order; 2.2.1 A Simple RC Filter2.2.2 Phase Lag-lead RRC or RCC Filter2.3 PLLs of the Second Order of Type 2; 2.3.1 PLLs of the Second Order of Type 2 with Voltage Output PD; 2.3.2 PLLs of the Second Order of Type 2 with Current Output Phase Detector; 2.4 Second-order PLLs with Frequency Dividers in the Feedback Path; References; 3 PLLs of the Third and Higher Orders; 3.1 General Open-loop Transfer Function G(s); 3.1.1 Additional RC Section; 3.1.2 Two RC Sections; 3.1.3 Active Second-order Low-pass Filter; 3.1.4 Twin-T RC Filter; 3.1.5 PLLs with a Selective Filter in the Feedback Path; 3.1.6 Time Delays in PLLs3.2 Higher-order Type 2 PLLs3.2.1 Third-order Loops: Lag-lead Filter with Additional RC Section; 3.2.2 Third-order Loop: Second-order Lag Filter Plus RC Section; 3.2.3 Fourth-order Loops; 3.2.4 Fifth-order Loops; 3.3 PLLs with Transmission Blocks in the Feedback Path; 3.3.1 Divider in the Feedback Path; 3.3.2 IF Filter in the Feedback Path; 3.3.3 IF Filter and Divider in the Feedback Path; 3.4 Sampled Higher-order Loops; 3.4.1 Third-order Loops with the Current Output Phase Detector; 3.5 Higher-order Loops of Type 3; 3.6 Computer Design of a Higher-order PLL; References4 Stability of the PLL Systems4.1 Hurwitz Criterion of Stability; 4.2 Computation of the Roots of the Polynomial P(s); 4.3 Expansion of the Function 1/[1 + G(s)] into a Sum of Simple Fractions; 4.3.1 Polynomial S(s) Contains Simple Roots Only; 4.3.2 Polynomial S(s) Contains a Pair of Complex Roots; 4.3.3 Polynomial S(s) Contains Multiple-order Roots; 4.4 The Root-locus Method; 4.5 Frequency Analysis of the Transfer Functions - Bode Plots; 4.5.1 Bode Plots; 4.5.2 Polar Diagrams; 4.6 Nyquist Criterion of Stability; 4.7 The Effective Damping Factor; 4.8 Appendix; References; 5 Tracking5.1 Transients in PLLs5.1.1 Transients in First-order PLLs; 5.1.2 Transients in Second-order PLLs; 5.1.3 Transients in Higher-order Loops; 5.2 Periodic Changes; 5.2.1 Phase Modulation of the Input Signal; 5.2.2 Frequency Modulation of the Input Signal; 5.3 Discrete Spurious Signals; 5.3.1 Small Discrete Spurious Signals at the Input; 5.3.2 Small Spurious Signals at the Output of the Phase Detector; 5.3.3 Small Spurious Signals at the Output of the PLLs; References; 6 Working Ranges of PLLs; 6.1 Hold-in Range; 6.1.1 Phase Detector with the Sine Wave Output; 6.1.2 The PD with Triangular Output6.1.3 The PD with a Sawtooth Wave OutputPhase lock loop frequency synthesis finds uses in a myriad of wireless applications - from local oscillators for receivers and transmitters to high performance RF test equipment. As the security and reliability of mobile communication transmissions have gained importance, PLL and frequency synthesisers have become increasingly topical subjects.Phase Lock Loops & Frequency Synthesis examines the various components that make up the phase lock loop design, including oscillators (crystal, voltage controlled), dividers and phase detectors. Interaction amongst the various components are also disPhase-locked loopsFrequency synthesizersPhase-locked loops.Frequency synthesizers.621.3815/364Kroupa Venceslav F.1923-845532MiAaPQMiAaPQMiAaPQBOOK9911018797603321Phase lock loops and frequency synthesis4417352UNINA