05483nam 2200733Ia 450 991100688710332120200520144314.097866117961129781281796110128179611597800805601130080560113(CKB)1000000000547636(EBL)404315(OCoLC)476217896(SSID)ssj0000157709(PQKBManifestationID)11167598(PQKBTitleCode)TC0000157709(PQKBWorkID)10140439(PQKB)11150799(MiAaPQ)EBC404315(PPN)170599698(OCoLC)801817727(OCoLC)ocn801817727 (FR-PaCSA)88812092(CaSebORM)9780750689748(FRCYB88812092)88812092(EXLCZ)99100000000054763620080509d2008 uy 0engur|n|---|||||txtccrFPGAs instant access /Clive "Max" Maxfield1st editionAmsterdam ;Boston Newnesc20081 online resource (217 p.)The Newnes instant access seriesIncludes index.9780750689748 0750689749 Front Cover; FPGAs: Instant Access; Copyright Page; Contents; About the Author; Chapter 1. The Fundamentals; Why Use FPGAs?; Applications; Some Technology Background; Fusible-link Technology; FPGA Programming Technologies; Instant Summary; Chapter 2. FPGA Architectures; More on Programming Technologies; SRAM-based Devices; Antifuse-based Devices; E[sup(2)]PROM/FLASH-based Devices; Hybrid FLASH-SRAM Devices; Fine-, Medium-, and Coarse-grained Architectures; Logic Blocks; MUX-based; LUT-based; LUT versus Distributed RAM versus SR; CLBs versus LABs versus Slices; Logic Cells/Logic ElementsSlicing and DicingCLBs and LABs; Distributed RAMs and Shift Registers; Embedded RAMs; Embedded Multipliers, Adders, etc.; Embedded Processor Cores; Hard Microprocessor Cores; Soft Microprocessor Cores; Clock Managers; Clock Trees; Clock Managers; General-purpose I/O; Configurable I/O Standards; Configurable I/O Impedances; Core versus I/O Supply Voltages; Gigabit Transceivers; Multiple Standards; Intellectual Property (IP); Handcrafted IP; IP Core Generators; System Gates versus Real Gates; Instant Summary; Chapter 3. Programming (Configuring) an FPGA; Configuration CellsAntifuse-based FPGAsSRAM-based FPGAs; Programming Embedded (Block) RAMs, Distributed RAMs, etc.; Multiple Programming Chains; Quickly Reinitializing the Device; Using the Configuration Port; Serial Load with FPGA as Master; Parallel Load with FPGA as Master; Parallel Load with FPGA as Slave; Serial Load with FPGA as Slave; Using the JTAG Port; Using an Embedded Processor; Instant Summary; Chapter 4. FPGA vs. ASIC Designs; When You Switch from ASIC to FPGA Design, or Vice Versa; Coding Styles; Pipelining and Levels of Logic; Levels of Logic; Asynchronous Design PracticesAsynchronous StructuresCombinational Loops; Delay Chains; Clock Considerations; Clock Domains; Clock Balancing; Clock Gating versus Clock Enabling; PLLs and Clock Conditioning Circuitry; Reliable Data Transfer across Multiclock Domains; Register and Latch Considerations; Latches; Flip-flops with both ""Set"" and ""Reset"" Inputs; Global Resets and Initial Conditions; Resource Sharing (Time-Division Multiplexing); Use It or Lose It!; But Wait, There's More; State Machine Encoding; Test Methodologies; Migrating ASIC Designs to FPGAs and Vice Versa; Alternative Design Scenarios; Instant SummaryChapter 5. ""Traditional"" Design FlowsSchematic-based Design Flows; Back-end Tools like Layout; CAE + CAD = EDA; A Simple (early) Schematic-driven ASIC Flow; A Simple (early) Schematic-driven FPGA Flow; Flat versus Hierarchical Schematics; Schematic-driven FPGA Design Flows Today; HDL-based Design Flows; Advent of HDL-based Flows; A Plethora of HDLs; Points to Ponder; Instant Summary; Chapter 6. Other Design Flows; C/C++-based Design Flows; C versus C++ and Concurrent versus Sequential; SystemC-based Flows; Augmented C/C++-based Flows; Pure C/C++ -based FlowsDifferent Levels of Synthesis AbstractionFPGAs are central to electronic design! The engineers designing these devices are in need of essential information at a moment's notice. The Instant Access Series provides all the critical content that a computer design engineer needs in his or her daily work. This book provides an introduction to FPGAs as well as succinct overviews of fundamental concepts and basic programming. FPGAs are a customizable chip flexible enough to be deployed in a wide range of products and applications. There are several basic design flows detailed including ones based in C/C++, DSP, and HDL. This book isNewnes instant access series.Field programmable gate arrays instant accessField programmable gate arraysGate array circuitsField programmable gate arrays.Gate array circuits.621.39/5Maxfield Clive1957-1607749MiAaPQMiAaPQMiAaPQBOOK9911006887103321FPGAs4391862UNINA