03980nam 2200661Ia 450 991096666980332120200520144314.097815969338421596933844(CKB)1000000000787510(EBL)456885(OCoLC)503447788(SSID)ssj0000137235(PQKBManifestationID)11144685(PQKBTitleCode)TC0000137235(PQKBWorkID)10087805(PQKB)10699572(Au-PeEL)EBL456885(CaPaEBR)ebr10312962(OCoLC)535923707(CaBNVSL)mat09100660(IEEE)9100660(MiAaPQ)EBC456885(Perlego)4667991(EXLCZ)99100000000078751020090117d2009 uy 0engur|n|---|||||txtccrDesign methodology for RF CMOS phase lock loops /Carlos Quemada, Guillermo Bistue, Inigo Adin1st ed.Boston ;London Artech Housec20091 online resource (242 p.)Artech House microwave libraryDescription based upon print version of record.9781596933835 1596933836 Includes bibliographical references and index.Design Methodology for RF CMOS Phase Locked Loops; Contents; Preface; 1 Approach to CMOS PLL Design; 2 PLL Fundamentals; 3 LC-Tank Integrated Oscillators; 4 Frequency Divider; 5 Phase Frequency Detector/Phase Detector; 6 Determination of Building Blocks Specifications; 7 Design of a 3.2-GHz CMOS VCO; 8 Design of a Frequency Divider; 9 Design of a Phase Frequency Detector; 10 Design of the Complete PLL; 11 PLL Characterization and Results; About the Authors; IndexBlast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.Publisher abstract.Artech House microwave library.Metal oxide semiconductors, ComplementaryDesign and constructionPhase-locked loopsDesign and constructionMetal oxide semiconductors, ComplementaryDesign and construction.Phase-locked loopsDesign and construction.621.3815/364Quemada Carlos1812998Adin IInigoigo1812999Bistue Guillermo1813000MiAaPQMiAaPQMiAaPQBOOK9910966669803321Design methodology for RF CMOS phase lock loops4365723UNINA