02190oam 2200385zu 450 991087261580332120210807003441.0(CKB)111055184224140(SSID)ssj0000454725(PQKBManifestationID)12195459(PQKBTitleCode)TC0000454725(PQKBWorkID)10397876(PQKB)11666437(NjHacI)99111055184224140(EXLCZ)9911105518422414020160829d2001 uy engur|||||||||||txtccr19th IEEE VLSI Test Symposium, 2001, Marina Del Rey, CA[Place of publication not identified]IEEE Computer Society Press20011 online resource (456 pages)Bibliographic Level Mode of Issuance: Monograph0-7695-1122-8 Collects 58 papers from the April/May 2001 symposium that explore new approaches in the testing of electronic circuits and systems. Key areas in testing are discussed, such as BIST, analog measurement, fault tolerance, diagnosis methods, scan chain design, memory test and diagnosis, and test data compression and compaction. Also on the program are sessions on emerging areas that are gaining prominence, including low power testing, testing high speed circuits on low cost testers, processor based self test techniques, and core- based system-on-chip testing. Some of the topics are robust and low cost BIST architectures for sequential fault testing in datapath multipliers, a method for measuring the cycle-to-cycle period jitter of high-frequency clock signals, fault equivalence identification using redundancy information and static and dynamic extraction, and test scheduling for minimal energy consumption under power constraints. No subject index. c. Book News Inc.Integrated circuitsVery large scale integrationCongressesIntegrated circuitsVery large scale integration621.395PQKBPROCEEDING991087261580332119th IEEE VLSI Test Symposium, 2001, Marina Del Rey, CA2324886UNINA