02006oam 2200397zu 450 991087244700332120241212215208.0(CKB)1000000000021582(SSID)ssj0000455444(PQKBManifestationID)12166222(PQKBTitleCode)TC0000455444(PQKBWorkID)10419544(PQKB)11549998(NjHacI)991000000000021582(EXLCZ)99100000000002158220160829d2002 uy engur|||||||||||txtccr17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002)[Place of publication not identified]IEEE Computer Society Press20021 online resource (456 pages)Bibliographic Level Mode of Issuance: Monograph9780769518312 0769518311 These 45 papers from the November 2002 symposium discuss techniques to assess and enhance the yield, reliability, and availability of VLSI systems. Several of the contributors present new approaches to fault simulation and injection, concurrent error detection, yield prediction, and sequential circuit design for testability. Specific topics include a simplified gate-level fault model for crosstalk effects analysis, input ordering in concurrent checkers to reduce power consumption, on-chip jitter measurement for phase locked loops, and a method to evaluate the repairability of embedded multiple regions DRAMs. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR.Integrated circuitsVery large scale integrationCongressesIntegrated circuitsVery large scale integration621.395PQKBPROCEEDING991087244700332117th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002)2372315UNINA