03100nam 22006374a 450 991045032210332120200520144314.00-429-23054-00-203-68702-71-134-88624-11-280-02558-10-203-35793-0(CKB)1000000000249437(EBL)199918(OCoLC)56549309(SSID)ssj0000294647(PQKBManifestationID)11193661(PQKBTitleCode)TC0000294647(PQKBWorkID)10312972(PQKB)10967154(MiAaPQ)EBC199918(Au-PeEL)EBL199918(CaPaEBR)ebr10098921(CaONFJC)MIL2558(EXLCZ)99100000000024943720031110d2004 uy 0engur|n|---|||||txtccrEconomics, economists, and expectations[electronic resource] microfoundations to macroapplications /Warren Young, Robert Leeson and William Darity, JnrLondon ;New York Routledge20041 online resource (177 p.)Routledge studies in the history of economics ;65Description based upon print version of record.0-415-64732-0 0-415-08515-2 Includes bibliographical references (p. [140]-155) and index.Book Cover; Title; Contents; Preface; Acknowledgments; Abbreviations; Introduction; From Hayek to Vernon Smith: prices, the cobweb, and game theory; The Hart Research Agenda: information, anticipation, and the firm; Expectations research projects: from Illinois to Carnegie Tech; Muth, Mills, and Tinbergen; December 1959 and its aftermath; Patinkin, expectations, and Chicago; Expectations and the monetarist counter-revolution; Overview and conclusions; Bibliography; IndexThe concept of rational expectations has played a hugely important role in economics over the years. Dealing with the origins and development of modern approaches to expectations in micro and macroeconomics, this book makes use of primary sources and previously unpublished material from such figures as Hicks, Hawtrey and Hart. The accounts of the 'founding fathers' of the models themselves are also presented here for the first time. The authors trace the development of different approaches to expectations from the likes of Hayek, Morgenstern, and Coase right up to more modern theorists suchRoutledge studies in the history of economics ;65.Rational expectations (Economic theory)Electronic books.Rational expectations (Economic theory)330/.01Young Warren1949-123432Leeson Robert144943Darity William A.1953-124556MiAaPQMiAaPQMiAaPQBOOK9910450322103321Economics, economists, and expectations1952224UNINA05817nam 22008293u 450 991082671410332120210107031200.0978661315735597812831573531283157357978111800991811180099169781118009925111800992497811180099011118009908(CKB)2550000000039100(EBL)693260(SSID)ssj0000521630(PQKBManifestationID)11913727(PQKBTitleCode)TC0000521630(PQKBWorkID)10523722(PQKB)11574996(OCoLC)746326310(CaSebORM)9780470643365(MiAaPQ)EBC693260(Perlego)1014342(EXLCZ)99255000000003910020131014d2011|||| u|| |engur|n|---|||||txtccrComputer System Design System-on-Chip1st editionHoboken Wiley20111 online resource (356 p.)Description based upon print version of record.9780470643365 0470643366 Includes bibliographical references (p. 316-328) and index.COMPUTER SYSTEM DESIGN; CONTENTS; PREFACE; LIST OF ABBREVIATIONS AND ACRONYMS; 1: Introduction to the Systems Approach; 1.1 SYSTEM ARCHITECTURE: AN OVERVIEW; 1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS; 1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE; 1.4 PROCESSOR ARCHITECTURES; 1.4.1 Processor: A Functional View; 1.4.2 Processor: An Architectural View; 1.5 MEMORY AND ADDRESSING; 1.5.1 SOC Memory Examples; 1.5.2 Addressing: The Architecture of Memory; 1.5.3 Memory for SOC Operating System; 1.6 SYSTEM-LEVEL INTERCONNECTION; 1.6.1 Bus-Based Approach1.6.2 Network-on-Chip Approach1.7 AN APPROACH FOR SOC DESIGN; 1.7.1 Requirements and Specifications; 1.7.2 Design Iteration; 1.8 SYSTEM ARCHITECTURE AND COMPLEXITY; 1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC; 1.9.1 Factors Affecting Product Costs; 1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC; 1.10 DEALING WITH DESIGN COMPLEXITY; 1.10.1 Buying IP; 1.10.2 Reconfiguration; 1.11 CONCLUSIONS; 1.12 PROBLEM SET; 2: Chip Basics: Time, Area, Power, Reliability, and Configurability; 2.1 INTRODUCTION; 2.1.1 Design Trade-Offs; 2.1.2 Requirements and Specifications2.2 CYCLE TIME2.2.1 Defining a Cycle; 2.2.2 Optimum Pipeline; 2.2.3 Performance; 2.3 DIE AREA AND COST; 2.3.1 Processor Area; 2.3.2 Processor Subunits; 2.4 IDEAL AND PRACTICAL SCALING; 2.5 POWER; 2.6 AREA-TIME-POWER TRADE-OFFS IN PROCESSOR DESIGN; 2.6.1 Workstation Processor; 2.6.2 Embedded Processor; 2.7 RELIABILITY; 2.7.1 Dealing with Physical Faults; 2.7.2 Error Detection and Correction; 2.7.3 Dealing with Manufacturing Faults; 2.7.4 Memory and Function Scrubbing; 2.8 CONFIGURABILITY; 2.8.1 Why Reconfigurable Design?; 2.8.2 Area Estimate of Reconfigurable Devices; 2.9 CONCLUSION2.10 PROBLEM SET3: Processors; 3.1 INTRODUCTION; 3.2 PROCESSOR SELECTION FOR SOC; 3.2.1 Overview; 3.2.2 Example: Soft Processors; 3.2.3 Examples: Processor Core Selection; 3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE; 3.3.1 Instruction Set; 3.3.2 Some Instruction Set Conventions; 3.3.3 Branches; 3.3.4 Interrupts and Exceptions; 3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE; 3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING; 3.5.1 The Instruction Decoder and Interlocks; 3.5.2 Bypassing; 3.5.3 Execution Unit; 3.6 BUFFERS: MINIMIZING PIPELINE DELAYS; 3.6.1 Mean Request Rate Buffers3.6.2 Buffers Designed for a Fixed or Maximum Request Rate3.7 BRANCHES: REDUCING THE COST OF BRANCHES; 3.7.1 Branch Target Capture: Branch Target Buffers (BTBs); 3.7.2 Branch Prediction; 3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR; 3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS; 3.9.1 Vector Functional Units; 3.10 VLIW PROCESSORS; 3.11 SUPERSCALAR PROCESSORS; 3.11.1 Data Dependencies; 3.11.2 Detecting Instruction Concurrency; 3.11.3 A Simple Implementation; 3.11.4 Preserving State with Out-of-Order Execution3.12 PROCESSOR EVOLUTION AND TWO EXAMPLESThe next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses thSystem-on-chipSystems on a chipSystems on a chipSystems on a chipElectrical & Computer EngineeringHILCCEngineering & Applied SciencesHILCCElectrical EngineeringHILCCSystems on a chip.Systems on a chip.Systems on a chip.Electrical & Computer EngineeringEngineering & Applied SciencesElectrical Engineering004.1Flynn Michael J727526Luk Wayne1682625AU-PeELAU-PeELAU-PeELBOOK9910826714103321Computer System Design4052888UNINA