01014nam0 2200289 450 00000588820060119110106.020051010d2000----km-y0itay50------baitaITy---m---001yyAnalisi del commercio elettronico per i prodotti agro-alimentariOriana PorroProf. Gian Paolo CesarettiNapoliIstituto Universitario Navale2000158 p.ill.30 cmTesi di Dottorato di ricerca in: Economia delle risorse alimentari e dell'ambiente XIII° cicloCommercio elettronicoAlimenti658.8002033820Porro,Oriana630400Cesaretti,Gian PaoloIstituto Universitario NavaleITUNIPARTHENOPE20051010RICAUNIMARC000005888TESI-2000/1NAVA12005Analisi del commercio elettronico per i prodotti agro-alimentari1206172UNIPARTHENOPE08347nam 22008535 450 99646596290331620230223060144.03-540-95948-310.1007/978-3-540-95948-9(CKB)1000000000575766(SSID)ssj0000318341(PQKBManifestationID)11226186(PQKBTitleCode)TC0000318341(PQKBWorkID)10307543(PQKB)11444973(DE-He213)978-3-540-95948-9(MiAaPQ)EBC3063922(PPN)132870762(EXLCZ)99100000000057576620100301d2009 u| 0engurnn|008mamaatxtccrIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation[electronic resource] 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers /edited by Lars Svensson, José Monteiro1st ed. 2009.Berlin, Heidelberg :Springer Berlin Heidelberg :Imprint: Springer,2009.1 online resource (XIII, 462 p.) Theoretical Computer Science and General Issues,2512-2029 ;5349Bibliographic Level Mode of Issuance: Monograph3-540-95947-5 Includes bibliographical references and index.Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope.This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.Theoretical Computer Science and General Issues,2512-2029 ;5349Logic designMicroprocessorsComputer architectureElectronic digital computers—EvaluationComputer arithmetic and logic unitsComputer storage devicesMemory management (Computer science)Electronic circuitsLogic DesignProcessor ArchitecturesSystem Performance and EvaluationArithmetic and Logic StructuresComputer Memory StructureElectronic Circuits and SystemsLogic design.Microprocessors.Computer architecture.Electronic digital computers—Evaluation.Computer arithmetic and logic units.Computer storage devices.Memory management (Computer science).Electronic circuits.Logic Design.Processor Architectures.System Performance and Evaluation.Arithmetic and Logic Structures.Computer Memory Structure.Electronic Circuits and Systems.620/.004202825536DAT 190fstubELT 272fstubSS 4800rvkSvensson Larsedthttp://id.loc.gov/vocabulary/relators/edtMonteiro Joséedthttp://id.loc.gov/vocabulary/relators/edtBOOK996465962903316Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation772134UNISA05292nam 2200793 450 991082047630332120230829065425.01-118-94759-21-118-94760-61-118-94761-4(CKB)3710000000478688(EBL)4040103(SSID)ssj0001552700(PQKBManifestationID)16170502(PQKBTitleCode)TC0001552700(PQKBWorkID)12813004(PQKB)11383852(PQKBManifestationID)15072999(PQKBWorkID)12946836(PQKB)21547371(MiAaPQ)EBC4040103(DLC) 2015030343(Au-PeEL)EBL4040103(CaPaEBR)ebr11113419(CaONFJC)MIL833106(OCoLC)926070937(MiAaPQ)EBC7104267(Au-PeEL)EBL7104267(JP-MeL)3000111443(EXLCZ)99371000000047868820151110h20162016 uy 0engur|n|---|||||txtccrChildren's intonation a framework for practice and research /Bill Wells, Professor, Department of Human Communication Sciences University of Sheffield, Joy Stackhouse, Professor, Department of Human Communication Sciences, University of SheffieldChichester, England :Wiley Blackwell,2016.20161 online resource (421 p.)Children's Speech and Literacy DifficultiesTHEi Wiley ebooksDescription based upon print version of record.1-118-94762-2 Includes bibliographical references at the end of each chapters and index.Machine generated contents note: Preface Foreword by John Local 1 Intonation 2 Turns 3 Topics and focus 4 Actions 5 Intonation in interaction profile 6 Infancy 7 Pre-school years 8 School years 9 Models 10 Speech, language and literary difficulties 11 Autism spectrum and learning difficulties 12 Hearing impairments References Appendices 1: Transcription conventions 2: Robin: background information 3: Intonation in interaction profile 4: Developmental phase model 5: Intonation processing model 6: Mick 7: Jacob 8: Ricky Index."Children's Intonation: A Framework for Practice and Research is a practical guide that focuses on the nature, causes and assessment of intonation problems for children and adolescents. Focusses on issues of the nature, causes and assessment of intonation problems in children Contains numerous transcribed extracts from real conversations involving children Includes a variety of clinical tools and models, including a tool for profiling children's intonation skills; a psycholinguistic model of intonation processing; an interactional perspective on intonation use; and a developmental phase model to explain typical and atypical intonation development Case studies throughout to illustrate key points and clinical application Each chapter includes activities for the reader to complete with keys to check answers."--Provided by publisher."Children's Intonation: A Framework for Practice and Research is a practical guide that focuses on the nature, causes and assessment of intonation problems for children and adolescents. Highlighting the importance of intonation for everyday conversational interaction and the implications of this for teaching and therapy contexts, this book addresses the following questions: - How and when do children learn to use intonation for the purposes of interaction? - As children get older, does intonation become more important or less important for communication? - How might intonation be used to support or compensate for other aspects of language? - What are the implications for practitioners, parents and caregivers when interacting with young children? Clinically oriented, this book explores these questions through case studies that cover a range of developmental communication difficulties including autism spectrum disorders, hearing impairment and specific speech and language difficulties. It provides readers with a tool for profiling children's intonation skills, a developmental phase model to explain typical and atypical intonation development, a psycholinguistic model of intonation processing, interactional perspectives on intonation use, and consideration of intonation in relation to both written and spoken language"-- Provided by publisher.Children's speech and literacy difficulties.THEi Wiley ebooks.Language disorders in childrenLinguisticsChildrenLanguageProsodic analysis (Linguistics)Language disorders in children.Linguistics.ChildrenLanguage.Prosodic analysis (Linguistics)618.92/855MED007000bisacshWells Bill(Clinical linguistics),1689726Stackhouse JoyMiAaPQMiAaPQMiAaPQBOOK9910820476303321Children's intonation4065004UNINA