01565nam0-22004811i-450-99000368021040332120001010000368021FED01000368021(Aleph)000368021FED0100036802120000920d18171820km-y0itay50------baitay-------001yyVictories conquetes desastres revers et guerres civiles des français de 1792 a 1815par Societe de militaires et de gens de lettreParisC.L.F. Panckoucke1817-18201800 monografieSOCIETE DE MILITAIRES ET DE GENS DE LETTRE381111ITUNINARICAUNIMARCBK990003680210403321SE 001.03.02-1DECSESE 001.03.02-2DECSESE 001.03.02-3DECSESE 001.03.02-4DECSESE 001.03.02-5DECSESE 001.03.02-6DECSESE 001.03.02-7DECSESE 001.03.02-8DECSESE 001.03.02-9DECSESE 001.03.02-10DECSESE 001.03.02-11DECSESE 001.03.02-12DECSESE 001.03.02-13DECSESE 001.03.02-14DECSESE 001.03.02-15DECSESE 001.03.02-16DECSESE 001.03.02-17DECSESE 001.03.02-18DECSEDECSEVictories conquetes desastres revers et guerres civiles des français de 1792 a 1815498720UNINAING0105930nam 2200853Ia 450 991080917490332120250318172315.09786613373892978111999573911199957369780470977972047097797397812833738901283373890978047097792704709779229781119995852111999585X(CKB)3460000000003457(EBL)675308(SSID)ssj0000482438(PQKBManifestationID)11296392(PQKBTitleCode)TC0000482438(PQKBWorkID)10526565(PQKB)11102905(Au-PeEL)EBL675308(CaPaEBR)ebr10510475(CaONFJC)MIL337389(OCoLC)729726229(CaSebORM)9780470688472(MiAaPQ)EBC675308(PPN)242964982(OCoLC)810071451(OCoLC)ocn810071451(Perlego)1014735(EXLCZ)99346000000000345720101129d2011 uy 0engurunu|||||txtccrVHDL for logic synthesis /Andrew Rushton3rd ed.Chichester, West Sussex, U.K. Wiley20111 online resource (486 p.)Description based upon print version of record.9780470688472 0470688475 Includes bibliographical references and index.VHDL FOR LOGIC SYNTHESIS; Contents; Preface; List of Figures; List of Tables; 1 Introduction; 1.1 The VHDL Design Cycle; 1.2 The Origins of VHDL; 1.3 The Standardisation Process; 1.4 Unification of VHDL Standards; 1.5 Portability; 2 Register-Transfer Level Design; 2.1 The RTL Design Stages; 2.2 Example Circuit; 2.3 Identify the Data Operations; 2.4 Determine the Data Precision; 2.5 Choose Resources to Provide; 2.6 Allocate Operations to Resources; 2.7 Design the Controller; 2.8 Design the Reset Mechanism; 2.9 VHDL Description of the RTL Design; 2.10 Synthesis Results; 3 Combinational Logic3.1 Design Units 3.2 Entities and Architectures; 3.3 Simulation Model; 3.4 Synthesis Templates; 3.5 Signals and Ports; 3.6 Initial Values; 3.7 Simple Signal Assignments; 3.8 Conditional Signal Assignments; 3.9 Selected Signal Assignment; 3.10 Worked Example; 4 Basic Types; 4.1 Synthesisable Types; 4.2 Standard Types; 4.3 Standard Operators; 4.4 Type Bit; 4.5 Type Boolean; 4.6 Integer Types; 4.7 Enumeration Types; 4.8 Multi-Valued Logic Types; 4.9 Records; 4.10 Arrays; 4.11 Aggregates, Strings and Bit-Strings; 4.12 Attributes; 4.13 More on Selected Signal Assignments; 5 Operators5.1 The Standard Operators 5.2 Operator Precedence; 5.3 Boolean Operators; 5.4 Comparison Operators; 5.5 Shifting Operators; 5.6 Arithmetic Operators; 5.7 Concatenation Operator; 6 Synthesis Types; 6.1 Synthesis Type System; 6.2 Making the Packages Visible; 6.3 Logic Types - Std_Logic_1164; 6.4 Numeric Types - Numeric_Std; 6.5 Fixed-Point Types - Fixed_Pkg; 6.6 Floating-Point Types - Float_Pkg; 6.7 Type Conversions; 6.8 Constant Values; 6.9 Mixing Types in Expressions; 6.10 Top-Level Interface; 7 Std_Logic_Arith; 7.1 The Std_Logic_Arith Package; 7.2 Contents of Std_Logic_Arith7.3 Type Conversions 7.4 Constant Values; 7.5 Mixing Types in Expressions; 8 Sequential VHDL; 8.1 Processes; 8.2 Signal Assignments; 8.3 Variables; 8.4 If Statements; 8.5 Case Statements; 8.6 Latch Inference; 8.7 Loops; 8.8 Worked Example; 9 Registers; 9.1 Basic D-Type Register; 9.2 Simulation Model; 9.3 Synthesis Model; 9.4 Register Templates; 9.5 Register Types; 9.6 Clock Types; 9.7 Clock Gating; 9.8 Data Gating; 9.9 Asynchronous Reset; 9.10 Synchronous Reset; 9.11 Registered Variables; 9.12 Initial Values; 10 Hierarchy; 10.1 The Role of Components; 10.2 Indirect Binding; 10.3 Direct Binding10.4 Component Packages 10.5 Parameterised Components; 10.6 Generate Statements; 10.7 Worked Examples; 11 Subprograms; 11.1 The Role of Subprograms; 11.2 Functions; 11.3 Operators; 11.4 Type Conversions; 11.5 Procedures; 11.6 Declaring Subprograms; 11.7 Worked Example; 12 Special Structures; 12.1 Tristates; 12.2 Finite State Machines; 12.3 RAMs and Register Banks; 12.4 Decoders and ROMs; 13 Test Benches; 13.1 Test Benches; 13.2 Combinational Test Bench; 13.3 Verifying Responses; 13.4 Clocks and Resets; 13.5 Other Standard Types; 13.6 Don't Care Outputs; 13.7 Printing Response Values13.8 Using TextIO to Read Data FilesMaking VHDL a simple and easy-to-use hardware description language Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using theVHSIC Hardware Description Language for logic synthesisVHDL (Computer hardware description language)Logic designData processingComputer-aided designVHDL (Computer hardware description language)Logic designData processing.Computer-aided design.621.39/5COM059000bisacshRushton Andrew771816MiAaPQMiAaPQMiAaPQBOOK9910809174903321VHDL for logic synthesis4006985UNINA