01584oam 2200421 450 991071692310332120211122124614.0(CKB)5470000002526968(OCoLC)1285958197(EXLCZ)99547000000252696820211122d2021 ua 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierWildfire management in the midst of the COVID-19 pandemic hearing before the Committee on Energy and Natural Resources, United States Senate, One Hundred Sixteenth Congress, second session, June 9, 2020Washington :U.S. Government Publishing Office,2021.1 online resource (iv, 129 pages) color illustrations, color mapsS. hrg. ;116-371Includes bibliographical references.Wildfire management in the midst of the COVID-19 pandemic WildfiresUnited StatesPreventionCOVID-19 (Disease)United StatesCOVID-19 Pandemic, 2020-United StatesFire fightersHealth and hygieneUnited StatesLegislative hearings.lcgftWildfiresPrevention.COVID-19 (Disease)COVID-19 Pandemic, 2020-Fire fightersHealth and hygieneGPOGPOGPOBOOK9910716923103321Wildfire management in the midst of the COVID-19 pandemic3454435UNINA05577nam 22006974a 450 991078454940332120200520144314.01-281-02320-597866110232010-08-052523-7(CKB)1000000000364721(EBL)300905(OCoLC)437182903(SSID)ssj0000243356(PQKBManifestationID)11193921(PQKBTitleCode)TC0000243356(PQKBWorkID)10322085(PQKB)11225737(Au-PeEL)EBL300905(CaPaEBR)ebr10179837(CaONFJC)MIL102320(CaSebORM)9780120884216(MiAaPQ)EBC300905(EXLCZ)99100000000036472120061205d2007 uy 0engur|n|---|||||txtccrSee MIPS run[electronic resource] /Dominic Sweetman2nd ed.San Francisco, Calif. Morgan Kaufmann Publishers/Elsevierc20071 online resource (513 p.)The Morgan Kaufmann Series in Computer Architecture and DesignDescription based upon print version of record.0-12-088421-6 Includes bibliographical references (p. 477-479) and index.Front Cover; See MIPS® Run; Copyright Page; Foreword; Contents; Preface; Style and Limits; Conventions; Acknowledgments; Chapter 1. RISCs and MIPS Architectures; 1.1 Pipelines; 1.2 The MIPS Five-Stage Pipeline; 1.3 RISC and CISC; 1.4 Great MIPS Chips of the Past and Present; 1.5 MIPS Compared with CISC Architectures; Chapter 2. MIPS Architecture; 2.1 A Flavor of MIPS Assembly Language; 2.2 Registers; 2.3 Integer Multiply Unit and Registers; 2.4 Loading and Storing: Addressing Modes; 2.5 Data Types in Memory and Registers; 2.6 Synthesized Instructions in Assembly Language2.7 MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions2.8 Basic Address Space; 2.9 Pipeline Visibility; Chapter 3. Coprocessor 0: MIPS Processor Control; 3.1 CPU Control Instructions; 3.2 Which Registers Are RelevantWhen?; 3.3 CPU Control Registers and Their Encoding; 3.4 CP0 Hazards-A Trap for the Unwary; Chapter 4. How CachesWork on MIPS Processors; 4.1 Caches and Cache Management; 4.2 How CachesWork; 4.3 Write-Through Caches in Early MIPS CPUs; 4.4 Write-Back Caches in MIPS CPUs; 4.5 Other Choices in Cache Design; 4.6 Managing Caches; 4.7 L2 and L3 Caches4.8 Cache Configurations for MIPS CPUs4.9 Programming MIPS32/64 Caches; 4.10 Cache Efficiency; 4.11 Reorganizing Software to Influence Cache Efficiency; 4.12 Cache Aliases; Chapter 5. Exceptions, Interrupts, and Initialization; 5.1 Precise Exceptions; 5.2 When Exceptions Happen; 5.3 Exception Vectors:Where Exception Handling Starts; 5.4 Exception Handling: Basics; 5.5 Returning from an Exception; 5.6 Nesting Exceptions; 5.7 An Exception Routine; 5.8 Interrupts; 5.9 Starting Up; 5.10 Emulating Instructions; Chapter 6. Low-level Memory Management and the TLB6.1 The TLB/MMU Hardware andWhat It Does6.2 TLB/MMU Registers Described; 6.3 TLB/MMU Control Instructions; 6.4 Programming the TLB; 6.5 Hardware-Friendly Page Tables and Refill Mechanism; 6.6 Everyday Use of the MIPS TLB; 6.7 Memory Management in a Simpler OS; Chapter 7. Floating-Point Support; 7.1 A Basic Description of Floating Point; 7.2 The IEEE 754 Standard and Its Background; 7.3 How IEEE Floating-Point Numbers Are Stored; 7.4 MIPS Implementation of IEEE 754; 7.5 Floating-Point Registers; 7.6 Floating-Point Exceptions/Interrupts; 7.7 Floating-Point Control: The Control/Status Register7.8 Floating-Point Implementation Register7.9 Guide to FP Instructions; 7.10 Paired-Single Floating-Point Instructions and the MIPS-3D ASE; 7.11 Instruction Timing Requirements; 7.12 Instruction Timing for Speed; 7.13 Initialization and Enabling on Demand; 7.14 Floating-Point Emulation; Chapter 8. Complete Guide to the MIPS Instruction Set; 8.1 A Simple Example; 8.2 Assembly Instructions andWhat They Mean; 8.3 Floating-Point Instructions; 8.4 Differences in MIPS32/64 Release 1; 8.5 Peculiar Instructions and Their Purposes; 8.6 Instruction Encodings; 8.7 Instructions by Functional GroupChapter 9. Reading MIPS Assembly LanguageThis second edition is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers' resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operatingMorgan Kaufmann Series in Computer Architecture and DesignMIPS (Computer architecture)RISC microprocessorsEmbedded computer systemsProgrammingMIPS (Computer architecture)RISC microprocessors.Embedded computer systemsProgramming.004.165Sweetman Dominic770599MiAaPQMiAaPQMiAaPQBOOK9910784549403321See MIPS run1572476UNINA