04585nam 22007094a 450 991077810680332120230721031817.066110298421-281-02984-X97866110298451-60750-261-5600-00-0368-41-4356-0867-4(CKB)1000000000479707(EBL)320319(OCoLC)476117136(SSID)ssj0000125683(PQKBManifestationID)11148142(PQKBTitleCode)TC0000125683(PQKBWorkID)10026924(PQKB)10644291(MiAaPQ)EBC320319(Au-PeEL)EBL320319(CaPaEBR)ebr10196594(CaONFJC)MIL102984(EXLCZ)99100000000047970720070525d2007 uy 0engur|n|---|||||txtccrCommunicating process architectures 2007[electronic resource] WoTUG-30 : proceedings of the 30th WoTUG Technical Meeting, 8-11 July 2007, University of Surrey, Guildford, United Kingdom /edited by Alistair A. McEwan ... [et al.]Amsterdam Fairfax, VA IOS Press20071 online resource (528 p.)Concurrent systems engineering series ;v. 65Description based upon print version of record.1-58603-767-6 Title page; Preface; Programme Committee; Additional Reviewers; Contents; Fine-Grain Concurrency; Communicating Process Architecture for Multicores; Lazy Exploration and Checking of CSP Models with CSPsim; The Core Language of Aldwych; JCSProB: Implementing Integrated Formal Specifications in Concurrent Java; Components with Symbolic Transition Systems: A Java Implementation of Rendezvous; Concurrent/Reactive System Design with Honeysuckle; CSP and Real-Time: Reality or Illusion?; Testing and Sampling Parallel Systems; Mobility in JCSP: New Mobile Channel and Mobile Process ModelsC++CSP2: A Many-to-Many Threading Model for Multicore ArchitecturesDesign Principles of the SystemCSP Software Framework; PyCSP - Communicating Sequential Processes for Python; A Process-Oriented Architecture for Complex System Modelling; Concurrency Control and Recovery Management for Open e-Business Transactions; trancell - An Experimental ETC to Cell BE Translator; A Versatile Hardware-Software Platform for In-Situ Monitoring Systems; High Cohesion and Low Coupling: The Office Mapping Factor; A Process Oriented Approach to USB Driver DevelopmentA Native Transterpreter for the LEGO Mindstorms RCXIntegrating and Extending JCSP; Hardware/Software Synthesis and Verification Using Esterel; Modeling and Analysis of the AMBA Bus Using CSP and B; A Step Towards Refining and Translating B Control Annotations to Handel-C; Towards the Formal Verification of a Java Processor in Event-B; Advanced System Simulation, Emulation and Test (ASSET); Development of a Family of Multi-Core Devices Using Hierarchical Abstraction; Domain Specific Transformations for Hardware Ray TracingA Reconfigurable System-on-Chip Architecture for Pico-Satellite MissionsTransactional CSP Processes; Algebras of Actions in Concurrent Processes; Using occam-pi Primitives with the Cell Broadband Engine; Shared-Memory Multi-Processor Scheduling Algorithms for CCSP; Compiling occam to C with Tock; Author IndexDeals with Computer Science and models of Concurrency. This title emphasizes on hardware/software co-design and the understanding of concurrency that results from these systems. It includes a range of papers on this topic, from the formal modeling of buses in co-design systems through to software simulation and development environments.Concurrent systems engineering series ;v. 65.Parallel processing (Electronic computers)Congressesoccam (Computer program language)CongressesTransputersCongressesComputer architectureCongressesParallel processing (Electronic computers)occam (Computer program language)TransputersComputer architecture004McEwan Alistair A1569523WoTUG Technical MeetingMiAaPQMiAaPQMiAaPQBOOK9910778106803321Communicating process architectures 20073842474UNINA