01915oam 2200565 450 991071181550332120190214104846.0(CKB)5470000002487930(OCoLC)680423912(OCoLC)657295584(OCoLC)1011839355(OCoLC)1022043381(EXLCZ)99547000000248793020101110d1995 ua 0engurbn||||a||||txtrdacontentcrdamediacrrdacarrierCrude oil exports hearing before the Committee on Resources, House of Representatives, One Hundred Fourth Congress, first session, on H.R. 70, a bill to permit exports of certain domestically produced crude oil, and for other purposes, May 9, 1995--Washington, DCWashington :U.S. Government Printing Office,1995.1 online resource (iv, 169 pages) illustrations"Serial no. 104-12."Includes bibliographical references.Crude oil exports Petroleum law and legislationUnited StatesExport marketingUnited StatesExport controlsUnited StatesExport controlsfastExport marketingfastPetroleum law and legislationfastUnited StatesfastLegislative hearings.lcgftPetroleum law and legislationExport marketingExport controlsExport controls.Export marketing.Petroleum law and legislation.OCLCEOCLCEOCLCQOCLCFOCLCQOCLCOOCLCQNJROCLCQGPOBOOK9910711815503321Crude oil exports3469146UNINA05858nam 2200853Ia 450 991081376320332120200520144314.097866134052729781283405270128340527X9781119991144111999114597811199911371119991137(CKB)3460000000003397(EBL)699356(SSID)ssj0000476978(PQKBManifestationID)11324981(PQKBTitleCode)TC0000476978(PQKBWorkID)10480703(PQKB)11377755(Au-PeEL)EBL699356(CaPaEBR)ebr10510714(OCoLC)714797081(CaSebORM)9781119992653(MiAaPQ)EBC699356(OCoLC)841331985(OCoLC)ocn841331985 (Perlego)1011027(EXLCZ)99346000000000339720101215d2011 uy 0engur|n|---|||||txtccrESD design and synthesis /Steven H. Voldman1st editionChichester, West Sussex, U.K. Wiley20111 online resource (292 p.)ESD seriesDescription based upon print version of record.9781119992653 1119992656 9780470685716 0470685719 Includes bibliographical references and index.ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O2.2.3 Core-Limited Peripheral I/O Design ArchitectureElectrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach. Look inside for extensive coverage ESD series.Electrostatic dischargeSemiconductorsProtectionIntegrated circuitsProtectionElectrostaticsAnalog electronic systemsDesign and constructionSemiconductorsProtection.Integrated circuitsProtection.Electrostatics.Analog electronic systemsDesign and construction.621.3815/2TEC008010bisacshVoldman Steven H872423MiAaPQMiAaPQMiAaPQBOOK9910813763203321ESD1958013UNINA