01780nam 2200361 450 991068799450332120230627110400.010.5772/intechopen.91110(CKB)5850000000050239(NjHacI)995850000000050239(EXLCZ)99585000000005023920230627d2022 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierNetwork-on-Chip Architecture, Optimization, and Design Explorations /Isiaka A. Alimi [and three others]London :IntechOpen,2022.1 online resource (110 pages) illustrations1-83968-159-4 Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.Network-on-Chip Networks on a chipNetworks on a chip.621.381531Alimi Isiaka A.1367700NjHacINjHaclBOOK9910687994503321Network-on-Chip3391387UNINA