02032nam0 2200385 i 450 MO1000049320231121125552.08883199839IT2005-12383 20120215d2004 ||||0itac50 baitaitz01i xxxe z01n˜La œcultura epistolare nell'Ottocento: sondaggi sulle lettere del CEODa cura di Giuseppe Antonelli, Carla Chiummo, Massimo Palermocon CD-ROM contenente i testi dei carteggiRomaBulzoni[2004]268 p.21 cmAtti della Giornata di studio tenuta a Siena nel 2004.Tit. sul dorso: ˜La œcultura epistolare nell'Ottocento.CFI0644827˜La œcultura epistolare nell'Ottocento.CFI0644827Lettere e carteggiItaliaSec. 19.FIRRMLC183803ILingua italianaSec. 19.Fonti epistolariFIRCFIC157009I856.20921Antonelli, Giuseppe <1970- >BVEV062651Chiummo, CarlaCFIV120747Palermo, MassimoCFIV143629ITIT-0120120215IT-RM0290 IT-FR0017 BIBLIOTECA ANGELICARM0290 Biblioteca umanistica Giorgio ApreaFR0017 NMO10000493Biblioteca umanistica Giorgio Aprea 52MAG 5/1166 52FLS0000270705 VMN RS A 2014061120140611 52MAG 5/1166*** 52DUP0009043085 VMB RS A 2020052120200521 52MAG 5/1166** 52FLS0000270725 VMN RS A 2016033020160330 52MAG 5/1166* 52FLS0000270715 VMB RS A 2020052120200521 52MAG 6/1166**** 52DUP0009045595 VMB RS A 2020100620201006 06 52Cultura epistolare nell'Ottocento: sondaggi sulle lettere del CEOD3611125UNICAS04079nam 22005895 450 991067825190332120251009075046.0981-19-8551-010.1007/978-981-19-8551-5(MiAaPQ)EBC7208088(Au-PeEL)EBL7208088(CKB)26189276000041(DE-He213)978-981-19-8551-5(PPN)269099182(EXLCZ)992618927600004120230301d2023 u| 0engurcnu||||||||txtrdacontentcrdamediacrrdacarrierBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach /by Xiaowei Li, Guihai Yan, Cheng Liu1st ed. 2023.Singapore :Springer Nature Singapore :Imprint: Springer,2023.1 online resource (318 pages)Print version: Li, Xiaowei Built-In Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design Singapore : Springer,c2023 9789811985508 Includes bibliographical references and index.Chapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion.With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not onlyoffers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs. .ComputersMicroprocessorsComputer architectureHardware Performance and ReliabilityComputer HardwareProcessor ArchitecturesComputers.Microprocessors.Computer architecture.Hardware Performance and Reliability.Computer Hardware.Processor Architectures.004.2Li Xiaowei1345886Yan GuihaiLiu ChengMiAaPQMiAaPQMiAaPQBOOK9910678251903321Built-in fault-tolerant computing paradigm for resilient large-scale chip design3374622UNINA