03959nam 2200493 450 991063247000332120231110220840.03-031-16027-4(MiAaPQ)EBC7146410(Au-PeEL)EBL7146410(CKB)25461615500041(PPN)266349730(EXLCZ)992546161550004120230408d2023 uy 0engurcnu||||||||txtrdacontentcrdamediacrrdacarrierLogic synthesis for VLSI-based combined finite state machines synthesis targeting ASICs, CPLDs and FPGAs /edited by Alexander Barkalov [and four others]Cham, Switzerland :Springer,[2023]©20231 online resource (305 pages)Lecture Notes in Electrical Engineering ;v.922Print version: Barkalov, Alexander Logic Synthesis for VLSI-Based Combined Finite State Machines Cham : Springer International Publishing AG,c2023 9783031160264 Includes bibliographical references and index.Intro -- Preface -- Contents -- Abbreviations -- 1 Control Algorithms and Finite State Machines -- 1.1 Methods of Implementation of Control Algorithms -- 1.2 Basic Models of Finite State Machines -- 1.3 Synthesis of Mealy FSM -- 1.4 Synthesis of Moore FSM -- 1.5 Synthesis of Microprogram Control Units -- 1.6 Background of Combined FSMs -- References -- 2 VLSI-based Logic Synthesis -- 2.1 Evaluation of Logic Elements -- 2.2 Logic Synthesis with ASICs -- 2.3 Logic Synthesis with CPLDs -- 2.4 Logic Synthesis with FPGAs -- References -- 3 ASIC-based Synthesis of CFSMs -- 3.1 Trivial Matrix Implementation -- 3.2 Structural Decomposition for Matrix CFSMs -- 3.3 PES-based Matrix Circuits of Moore FSMs -- 3.4 Analysis of CFSM-based Matrix Circuits -- References -- 4 Optimization of ASIC-based CFSMs -- 4.1 CFSMs with Optimal State Assignment -- 4.2 CFSMs with Transformation of State Codes -- 4.3 CFSMs with Partial Code Transformation -- 4.4 CFSMs with Primary Encoding of Classes of PES -- References -- 5 Homogenous CPLD-Based Synthesis of CFSMs -- 5.1 Preliminary Information -- 5.2 Synthesis of P CFSM -- 5.3 Synthesis of CFSMs with Optimal State Assignment -- 5.4 Synthesis of CFSMs with Transformation of State Codes -- 5.5 Synthesis of CFSMs with Primary Encoding of Classes -- References -- 6 Heterogeneous CPLD-based Synthesis of CFSMs -- 6.1 Preliminary Information -- 6.2 Synthesis of CFSMs with Trivial State Assignment -- 6.3 Synthesis of CFSMs with Optimal State Assignment -- 6.4 Synthesis of CFSMs with Primary Encoding of Classes -- 6.5 Synthesis of CFSMs with Transformation of Object Codes -- References -- 7 CPLD-Based Synthesis with Transformation of State Codes -- 7.1 Synthesis with Complete State Transformation -- 7.2 Partial State Transformation: Homogenous CPLDs -- 7.3 Partial State Transformation: Heterogenous CPLDs.7.4 Combining Different Methods of Object Transformation -- References -- 8 FPGA-Based Synthesis of CFSMs -- 8.1 Preliminary Information -- 8.2 Primary Encoding of Classes of PES for FPGA-Based GFSMs -- 8.3 FPGA-Based Synthesis with Transformation of Class Codes -- 8.4 Twofold State Assignment in CFSMs -- References -- Appendix Conclusion -- Index.Lecture Notes in Electrical Engineering Integrated circuitsVery large scale integrationAutomatic controlSequential machine theoryIntegrated circuitsVery large scale integration.Automatic control.Sequential machine theory.629.8Barkalov AlexanderMiAaPQMiAaPQMiAaPQBOOK9910632470003321Logic synthesis for VLSI-based combined finite state machines3084146UNINA