03607nam 2200637 450 991048050790332120170822144209.01-4704-0212-2(CKB)3360000000464807(EBL)3114419(SSID)ssj0000889186(PQKBManifestationID)11488396(PQKBTitleCode)TC0000889186(PQKBWorkID)10875644(PQKB)11695185(MiAaPQ)EBC3114419(PPN)195415078(EXLCZ)99336000000046480719970908h19981998 uy| 0engur|n|---|||||txtccrRelations related to betweenness their structure and automorphisms /S.A. Adeleke, Peter M. NeumannProvidence, Rhode Island :American Mathematical Society,[1998]©19981 online resource (141 p.)Memoirs of the American Mathematical Society,0065-9266 ;number 623"January 1998, volume 131, number 623 (third of 4 numbers)."0-8218-0623-8 Includes bibliographical references.""CONTENTS""; ""PART I. PREPARATION""; ""1 Introduction""; ""2 Terminology and notation""; ""3 Linear relational structures""; ""PART II: SEMILINEAR ORDER RELATIONS""; ""4 Semilinearly ordered sets""; ""5 Examples of semilinear orderings""; ""6 Automorphism groups of semilinear orderings""; ""7 Maximal chains in semilinear orderings""; ""8 Piecewise linear maximal chains in semilinear orderings""; ""9 Enriching a semilinear ordering""; ""PART III: ABSTRACT CHAIN SETS""; ""10 C-relations""; ""11 Examples of C-sets""; ""12 The classification of C-sets""; ""13 A topology for C-sets""""14 Automorphism groups of C-sets""""PART IV. GENERAL BETWEENNESS RELATIONS""; ""15 B-relations and general betweenness relations""; ""16 Lines, half-lines and directions in a B-set""; ""17 The relationship between B-sets and semilinear orderings""; ""18 Components of B-sets""; ""19 Branch points and sectors of B-sets""; ""20 Automorphism groups of B-sets""; ""21 Improving a B-relation to a betweenness relation""; ""PART V: ABSTRACT DIRECTION SETS""; ""22 D-relations""; ""23 Examples of D-sets""; ""24 Structural partitions""; ""25 Linking of structural partitions""""26 The betweenness relation derived from a D-relation""""27 The topology on a D-set""; ""28 Automorphism groups of D-sets""; ""PART VI: APPLICATIONS AND COMMENTARY""; ""29 Combinatorial trees and discrete B-sets""; ""30 Arboreal group theory""; ""31 B-relations and topological spaces""; ""32 Cameron's tree-like objects""; ""33 B-relations and partially ordered sets""; ""34 Configurations of sets, with applications to permutation groups""; ""REFERENCES""Memoirs of the American Mathematical Society ;no. 623.Ordered algebraic structuresBetweenness relations (Mathematics)AutomorphismsPermutation groupsElectronic books.Ordered algebraic structures.Betweenness relations (Mathematics)Automorphisms.Permutation groups.510 s511.3/3Adeleke S. A(Samson Adepoju),1952-890442Neumann P. M.MiAaPQMiAaPQMiAaPQBOOK9910480507903321Relations related to betweenness1989076UNINA03476oam 2200397zu 450 99619954190331620210806235851.01-5090-9725-2(CKB)1000000000036025(SSID)ssj0000453730(PQKBManifestationID)12203628(PQKBTitleCode)TC0000453730(PQKBWorkID)10486352(PQKB)11345545(NjHacI)991000000000036025(EXLCZ)99100000000003602520160829d2005 uy engur|||||||||||txtccr2005 IEEE International High Level Design Validation and Test Workshop[Place of publication not identified]I E E E20051 online resource (viii, 250 pages) illustrationsBibliographic Level Mode of Issuance: Monograph0-7803-9571-9 Simulation-based functional test generation for embedded processors,"C. -- Scalable defect mapping and configuration of memory-based nanofabrics,"Chen -- Improvement of fault injection techniques based on VHDL code modification,"J. -- MVP: a mutation-based validation paradigm,"J. -- Establishing latch correspondence for embedded circuits of PowerPC microprocessors,"H. -- Sequential equivalence checking based on k-th invariants and circuit SAT solving,"Feng -- VERISEC: verifying equivalence of sequential circuits using SAT,"M. -- Automated clock inference for stream function-based system level specifications,"J. -- Cosimulation of ITRON-based embedded software with SystemC,"S. -- A software test program generator for verifying system-on-chips,"A. -- Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model,"Che-Hua -- DVGen: a test generator for the transmeta Efficeon VLIW processor,"K. -- Reuse in system-level stimuli-generation,"Y. -- Harnessing machine learning to improve the success rate of stimuli generation,"S. -- A new simulation-based property checking algorithm based on partitioned alternative search space traversal,"Qingwei -- Validating families of latency insensitive protocols,"S. -- GASIM: a fast Galois field based simulator for functional model,"D. -- Overlap reduction in symbolic system traversal,"P. -- Formal verification of high-level conformance with symbolic simulation,"R. -- A method for generation of GSTE assertion graphs,"E. -- Automatic abstraction refinement for Petri nets verification,"Zhenyu -- An optimum algorithm for compacting error traces for efficient functional debugging,"Chia-Chih -- Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking,"V. -- B-cubing theory: new possibilities for efficient SAT-solving,"D. -- Multilevel design validation in a secure embedded system,"D. -- Security evaluation against electromagnetic analysis at design time,"Huiyun -- Formal meaning of coverage metrics in simulation-based hardware design verification,"I. -- Advanced analysis techniques for cross-product coverage,"H. -- A proof of correctness for the construction of property monitors,".Computer softwareVerificationCongressesComputer softwareVerification005.14PQKBPROCEEDING9961995419033162005 IEEE International High Level Design Validation and Test Workshop2341855UNISA