04908nam 2200637Ia 450 991046521040332120200520144314.01-61209-883-5(CKB)2560000000070882(EBL)3017983(SSID)ssj0000474270(PQKBManifestationID)11342429(PQKBTitleCode)TC0000474270(PQKBWorkID)10453817(PQKB)10745054(MiAaPQ)EBC3017983(Au-PeEL)EBL3017983(CaPaEBR)ebr10658905(OCoLC)923654556(EXLCZ)99256000000007088220090113d2009 uy 0engur|n|---|||||txtccrVLSI and computer architecture[electronic resource] /Kenzo Watanabe, editorNew York Nova Science Publisherc20091 online resource (253 p.)Description based upon print version of record.1-60692-075-8 Includes bibliographical references and index.""VLSI AND COMPUTERARCHITECTURE""; ""VLSI AND COMPUTER ARCHITECTURE ""; ""CONTENTS""; ""PREFACE""; ""DESIGN CONSIDERATIONS AND ALGORITHMSFOR BROADBAND FIXED WIMAX SYSTEMS""; ""Abstract""; ""1. Introduction""; ""1.1. Introduction""; ""1.2. Orthogonal Frequency Division Multiplexing (OFDM)""; ""1.2.1. Non-iterative OFDM Scheme""; ""1.2.2. Iterative OFDM Scheme""; ""1.3. SC-FDE""; ""1.4. Quantitative Results""; ""2. Time-Domain Solutions""; ""2.1. Time-Domain Turbo Equalization for SISO System""; ""2.1.1. Initial stage""; ""2.1.2. Subsequent Stages""; ""2.1.3. Complexity Comparison""""2.2. Time-Domain Turbo Equalization for MIMO Systems""""2.2.1. Initial Stage""; ""2.2.2. Subsequent Stages""; ""2.3. Performance Comparison""; ""3. Conclusions""; ""References""; ""VLSI INTERCONNECTS AND THEIR DELAYPERFORMANCE""; ""Abstract""; ""1. Introduction""; ""2. Modeling Interconnect as RC & RLC Circuits""; ""2.1. Lumped and Distributed Models""; ""3. Extraction of Interconnect Parasitics""; ""4. Propagation Delay through Driver Interconnect Load Model""; ""4.1. Driver Delay Models""; ""4.2. Interconnect Delay Models""; ""4.3. Composite Driver-Interconnect-Load Model-A Case Study""""4.3.1. Effect of Short-Circuit Current on Propagation Delay""""4.3.2. Fifty Percent Propagation Delay Evaluation""; ""5. Delay Minimization Techniques""; ""6. Conclusion""; ""References""; ""DEVELOPMENT, VALIDATION AND EVALUATION OF ASPACE QUALIFIED LONG-LIFE FLIGHTCOMPUTER SERVER""; ""Abstract""; ""1. Introduction""; ""2. Single Board Microcomputers""; ""3. Fault Protections For Single Board Microcomputers""; ""3.1 Protections Against Seu Events""; ""3.2 Latch-Up Protection""; ""3.3 Other Protections""; ""4. Sqllcs Integration And Validation""""4.1 Hardware And Software Tools Developed For Sqllcs Validation""""4.2 Satellite Simulator""; ""4.3 SOFDEVO Software""; ""4.4 Earth Station Software""; ""5. Reliability Study Of Sqllcs Hardware""; ""5.1 SQLLCS Maintenance""; ""5.2 Reliability of an SQLLCS Assembled with Three SBMs""; ""5.3 Reliability for a Single SBM""; ""5.4 Reliability for a SQLLCS Assembled with Two SBMs""; ""6. Conclusion""; ""Acknowledgments""; ""References""; ""NUMERICAL SIMULATION OF QUANTUMWAVEGUIDES""; ""Abstract""; ""1. Introduction""""2. Transparent Boundary Conditions for the Two DimensionalSchrÂ?odinger Equation""""3. Discrete Transparent Boundary Conditions for the Two DimensionalSchrÂ?odinger Equation""; ""3.1. The Difference Equations""; ""3.2. Derivation of DTBCs for the Two Dimensional SchrÂ?odinger Equation""; ""3.3. Approximation of the DTBCs by Sums of Exponentials""; ""3.4. Fast Evaluation of the Discrete Convolution""; ""3.5. Implementation of the DTBCs""; ""4. Numerical Results""; ""4.1. Travelling GaussianWave Functions""; ""4.2. QuantumWaveguide Simulation""; ""Conclusion""; ""Acknowledgements""""References""Integrated circuitsVery large scale integrationDesign and constructionComputer architectureWireless communication systemsEquipment and suppliesDesign and constructionMicrocontrollersDesign and constructionElectronic books.Integrated circuitsVery large scale integrationDesign and construction.Computer architecture.Wireless communication systemsEquipment and suppliesDesign and construction.MicrocontrollersDesign and construction.621.39/5Watanabe Kenzo874524MiAaPQMiAaPQMiAaPQBOOK9910465210403321VLSI and computer architecture1952690UNINA