03313nam 22006252 450 991045450500332120151005020621.01-107-19643-41-282-39124-00-511-64683-697866123912480-511-62691-60-511-57932-20-511-65091-40-511-57858-X0-511-58006-1(CKB)1000000000784176(EBL)451928(OCoLC)551852806(SSID)ssj0000341710(PQKBManifestationID)11252607(PQKBTitleCode)TC0000341710(PQKBWorkID)10394648(PQKB)10928231(UkCbUP)CR9780511626913(MiAaPQ)EBC451928(Au-PeEL)EBL451928(CaPaEBR)ebr10333203(CaONFJC)MIL239124(EXLCZ)99100000000078417620090916d2009|||| uy| 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierPractical design verification /edited by Dhiraj K. Pradhan, Ian G. Harris[electronic resource]Cambridge :Cambridge University Press,2009.1 online resource (xi, 276 pages) digital, PDF file(s)Title from publisher's bibliographic system (viewed on 05 Oct 2015).0-521-85972-7 Includes bibliographical references and index.Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva.Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).Integrated circuitsVerificationIntegrated circuitsVerification.621.3815/48Pradhan Dhiraj K.Harris Ian G.UkCbUPUkCbUPBOOK9910454505003321Practical design verification2465880UNINA