03600nam 2200625 a 450 991043805020332120200520144314.01-283-64077-590-481-9644-210.1007/978-90-481-9644-9(CKB)3400000000086400(EBL)1030225(OCoLC)811773504(SSID)ssj0000766987(PQKBManifestationID)11445962(PQKBTitleCode)TC0000766987(PQKBWorkID)10739607(PQKB)10868799(DE-He213)978-90-481-9644-9(MiAaPQ)EBC1030225(PPN)168335204(EXLCZ)99340000000008640020120705d2013 uy 0engur|n|---|||||txtccrDesign, analysis and test of logic circuits under uncertainty /Smita Krishnaswamy, Igor L. Markov, John P. Hayes1st ed. 2013.New York Springer20131 online resource (129 p.)Lecture notes in electrical engineering,1876-1100 ;v. 115Description based upon print version of record.94-007-9798-2 90-481-9643-4 Includes bibliographical references and index.Introduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions.Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;   • Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;   • Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.Lecture Notes in Electrical Engineering,1876-1100 ;115Logic circuitsUncertainty (Information theory)Logic circuits.Uncertainty (Information theory)621.395Krishnaswamy Smita1060838Markov Igor L1750207Hayes John P(John Patrick),1944-1762476MiAaPQMiAaPQMiAaPQBOOK9910438050203321Design, analysis and test of logic circuits under uncertainty4202462UNINA