02541nam 2200553 a 450 991043792160332120200520144314.01-283-74045-11-4614-2410-010.1007/978-1-4614-2410-9(CKB)2670000000277993(EBL)1030859(OCoLC)818413973(SSID)ssj0000797953(PQKBManifestationID)11510587(PQKBTitleCode)TC0000797953(PQKBWorkID)10738687(PQKB)10013085(DE-He213)978-1-4614-2410-9(MiAaPQ)EBC1030859(PPN)168296330(EXLCZ)99267000000027799320120710d2013 uy 0engur|n|---|||||txtccrUTLEON3 exploring fine-grain multi-threading in FPGAs /Martin Danek ... [et al.]New York Springer20131 online resource (228 p.)Description based upon print version of record.1-4614-2409-7 Includes bibliographical references and index.pt. 1. Programming interface -- pt. 2. Implementation.This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.  Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language.    .Threads (Computer programs)Field programmable gate arraysThreads (Computer programs)Field programmable gate arrays.621.395Danek Martin1058215MiAaPQMiAaPQMiAaPQBOOK9910437921603321UTLEON32497942UNINA