03975nam 22005895 450 991036658000332120200701040427.03-030-31310-710.1007/978-3-030-31310-4(CKB)5280000000190185(MiAaPQ)EBC6000724(DE-He213)978-3-030-31310-4(PPN)242820352(EXLCZ)99528000000019018520191220d2020 u| 0engurcnu||||||||txtrdacontentcrdamediacrrdacarrierDesign and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures[electronic resource] /by Kanchan Manna, Jimson Mathew1st ed. 2020.Cham :Springer International Publishing :Imprint: Springer,2020.1 online resource3-030-31309-3 Includes bibliographical references and index.Introduction to Network-on-Chip Designs and Tests -- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems -- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems -- Temperature-aware design strategy for 3D-NoC-based multicore systems -- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems.This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.Electronic circuitsMicroprocessorsElectronicsMicroelectronicsCircuits and Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/T24068Processor Architectureshttps://scigraph.springernature.com/ontologies/product-market-codes/I13014Electronics and Microelectronics, Instrumentationhttps://scigraph.springernature.com/ontologies/product-market-codes/T24027Electronic circuits.Microprocessors.Electronics.Microelectronics.Circuits and Systems.Processor Architectures.Electronics and Microelectronics, Instrumentation.621.381531Manna Kanchanauthttp://id.loc.gov/vocabulary/relators/aut1062637Mathew Jimsonauthttp://id.loc.gov/vocabulary/relators/autMiAaPQMiAaPQMiAaPQBOOK9910366580003321Design and Test Strategies for 2D2527186UNINA