01842nam 2200397 450 991034935830332120231209100037.00-7381-4524-610.1109/IEEESTD.2004.95753(CKB)4100000009825462(NjHacI)994100000009825462(EXLCZ)99410000000982546220231209d2004 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierBehavioural languagesPart 4Verilog hardware description language /Institute of Electrical and Electronics EngineersNew York, New York :IEEE,2004.1 online resourceIEEE Std ;1364The Verilog(R) Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.IEEE Std ;1364.61691-4-2004 - IEC 61691-4 Ed.1 Verilog (Computer hardware description language)VHDL (Computer hardware description language)Verilog (Computer hardware description language)VHDL (Computer hardware description language)621.392NjHacINjHaclDOCUMENT9910349358303321Behavioural languages3646683UNINA