01484nam 2200349 450 991034935800332120231209100043.00-7381-4777-X10.1109/IEEESTD.2002.8894283(CKB)4100000009825465(NjHacI)994100000009825465(EXLCZ)99410000000982546520231209d2002 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrier62142-2005 - IEC/IEEE iInternational standard - Verilog(R) Register Transfer Level synthesis /Institute of Electrical and Electronics EngineersNew York, New York :IEEE,2002.1 online resource (116 pages)Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.62142-2005 - IEC/IEEE International Standard - VerilogVHDL (Computer hardware description language)VHDL (Computer hardware description language)621.392NjHacINjHaclDOCUMENT991034935800332162142-2005 - IEC2581352UNINA