00923nam0 22002653i 450 VAN013144620201020024704.708IT1956 482320201020d1955 |0itac50 baitaIT|||| |||||Saggi di diritto penalecalunnia-tentativoLuigi GulloMilano : Giuffrè, 1955144 p.26 cmFondo Avellino.MilanoVANL000284GulloLuigiVANV105203225174Giuffrè <editore>VANV109181650ITSOL20230616RICABIBLIOTECA DEL DIPARTIMENTO DI GIURISPRUDENZAIT-CE0105VAN00VAN0131446BIBLIOTECA DEL DIPARTIMENTO DI GIURISPRUDENZA00CONS AV.16 00UBG5614 20201020 Saggi di diritto penale586296UNICAMPANIA04080nam 22005415 450 991033764980332120200703050546.03-319-98116-110.1007/978-3-319-98116-1(CKB)4100000006098284(MiAaPQ)EBC5507952(DE-He213)978-3-319-98116-1(PPN)230542395(EXLCZ)99410000000609828420180901d2019 u| 0engurcnu||||||||txtrdacontentcrdamediacrrdacarrierPost-Silicon Validation and Debug /edited by Prabhat Mishra, Farimah Farahmandi1st ed. 2019.Cham :Springer International Publishing :Imprint: Springer,2019.1 online resource (393 pages)3-319-98115-3 Part 1. Introduction -- Post-Silicon SoC Validation Challenges -- Part 2. Debug Infrastructure -- SoC Instrumentations: Pre-silicon Preparation for Post-silicon Readiness -- Structure-based Signal Selection for Post-silicon Validation -- Simulation-based Signal Selection -- Hybrid Signal Selection -- Post-Silicon Signal Selection using Machine Learning -- Part 3. Generation of Tests and Assertions -- Observability-aware Post-Silicon Test Generation -- On-chip Constrained-Random Stimuli Generation -- Test Generation and Lightweight Checking for Multi-core Memory Consistency -- Selection of Post-Silicon Hardware Assertions -- Part 4. Post-Silicon Debug -- Debug Data Reduction Techniques -- High-level Debugging of Post-silicon Failures -- Post-silicon Fault Localization with Satisfiability Solvers -- Coverage Evaluation and Analysis of Post-silicon Tests with Virtual Prototypes -- Utilization of Debug Infrastructure for Post-Silicon Coverage Analysis -- Part 5. Case Studies -- Network-on-Chip Validation and Debug -- Post-silicon Validation of the IBM Power8 Processor -- Part 6. Conclusion and Future Directions -- SoC Security versus Post-Silicon Debug Conflict -- The Future of Post-Silicon Debug.This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. Provides a comprehensive overview of the SoC post-silicon validation and debug challenges; Covers state-of-the-art techniques for developing on-chip debug infrastructure; Describes automated techniques for generating post-silicon tests and assertions to enable effective post-silicon debug and coverage analysis; Covers scalable post-silicon validation and bug localization using a combination of simulation-based techniques and formal methods; Presents case studies for post-silicon debug of industrial SoC designs.Electronic circuitsMicroprocessorsElectronicsMicroelectronicsCircuits and Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/T24068Processor Architectureshttps://scigraph.springernature.com/ontologies/product-market-codes/I13014Electronics and Microelectronics, Instrumentationhttps://scigraph.springernature.com/ontologies/product-market-codes/T24027Electronic circuits.Microprocessors.Electronics.Microelectronics.Circuits and Systems.Processor Architectures.Electronics and Microelectronics, Instrumentation.005.14Mishra Prabhatedthttp://id.loc.gov/vocabulary/relators/edtFarahmandi Farimahedthttp://id.loc.gov/vocabulary/relators/edtBOOK9910337649803321Post-Silicon Validation and Debug2177702UNINA