04309nam 22007455 450 991029949490332120200701171226.03-319-04942-910.1007/978-3-319-04942-7(CKB)2670000000548028(EBL)1698173(OCoLC)881166040(SSID)ssj0001186936(PQKBManifestationID)11787425(PQKBTitleCode)TC0001186936(PQKBWorkID)11240598(PQKB)11642382(MiAaPQ)EBC1698173(DE-He213)978-3-319-04942-7(PPN)177822198(EXLCZ)99267000000054802820140321d2014 u| 0engur|n|---|||||txtccrScalable and Near-Optimal Design Space Exploration for Embedded Systems /by Angeliki Kritikakou, Francky Catthoor, Costas Goutis1st ed. 2014.Cham :Springer International Publishing :Imprint: Springer,2014.1 online resource (287 p.)Description based upon print version of record.3-319-04941-0 Includes bibliographical references and index.Introduction & Motivation -- Reusable DSE methodology for scalable & near-optimal frameworks -- Part I Background memory management methodologies -- Development of intra-signal in-place methodology -- Pattern representation -- Intra-signal in-place methodology for non-overlapping scenario -- Intra-signal in-place methodology for overlapping scenario -- Part II Processing related mapping methodologies -- Design-time scheduling techniques DSE framework -- Methodology to develop design-time scheduling techniques under constraints -- Design Exploration Methodology for Microprocessor & HW accelerators -- Conclusions & Future Directions.This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies.  The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems.  Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.   • Describes design space exploration (DSE) methodologies for data storage and processing in embedded systems, which achieve near-optimal solutions with scalable exploration time; • Presents a set of principles and the processes which support the development of the proposed scalable and near-optimal methodologies; • Enables readers to apply scalable and near-optimal methodologies to the intra-signal in-place optimization step for both regular and irregular memory accesses.Electronic circuitsMicroprocessorsElectronicsMicroelectronicsEnergyCircuits and Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/T24068Processor Architectureshttps://scigraph.springernature.com/ontologies/product-market-codes/I13014Electronics and Microelectronics, Instrumentationhttps://scigraph.springernature.com/ontologies/product-market-codes/T24027Energy, generalhttps://scigraph.springernature.com/ontologies/product-market-codes/100000Electronic circuits.Microprocessors.Electronics.Microelectronics.Energy.Circuits and Systems.Processor Architectures.Electronics and Microelectronics, Instrumentation.Energy, general.004.1006.2/2620621.042Kritikakou Angelikiauthttp://id.loc.gov/vocabulary/relators/aut873967Catthoor Franckyauthttp://id.loc.gov/vocabulary/relators/autGoutis Costasauthttp://id.loc.gov/vocabulary/relators/autBOOK9910299494903321Scalable and Near-Optimal Design Space Exploration for Embedded Systems1951239UNINA