01103nam2 22002533i 450 UM1009094520231121125910.020161109d2000 ||||0itac50 balatitz01i xxxe z01n8.3: Fontes. ORomaeapud Istituto storico italiano per il Medioevo2000P. 310-43628 cm.001CFI00183672001 Repertorium fontium historiae Medii Aeviprimum ab Augusto Potthast digestumnunc cura Collegii historicorum e pluribus nationibus emendatum et auctum[a cura di] Istituto storico italiano per il Medio Evo; Unione internazionale degli istituti di archeologia, storia e storia dell'arte di Roma8.3ITIT-0120161109IT-FR0017 Biblioteca umanistica Giorgio ApreaFR0017 NUM10090945Biblioteca umanistica Giorgio Aprea 52MAG 8 Coll E-8.3 52MAG0000241995 VMN RS A 2016110920161109 52Fontes887165UNICAS03716oam 2200517 450 991029948780332120190911103512.01-4614-8310-710.1007/978-1-4614-8310-6(OCoLC)872698957(MiFhGG)GVRL6XTO(EXLCZ)99371000000002485320130808d2014 uy 0engurun|---uuuuatxtccrTurbo decoder architecture for beyond-4G applications /Cheng-Chi Wong, Hsie-Chia Chang1st ed. 2014.New York :Springer,2014.1 online resource (viii, 100 pages) illustrationsGale eBooksDescription based upon print version of record.1-4614-8309-3 Includes bibliographical references.Introduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture.This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications.  The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time.  Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. Several state-of-the-art techniques that improve complexity and/or throughput are introduced.  The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards and enables designs that reconfigure block size and parallelism.  Case studies include the discussions of both throughput and performance of each mode (block size/parallelism/iteration).  This book not only highlights the critical design issues that restrict the speedup of parallel architecture, but it also provides the solutions to overcome these limitations by modifying slightly the turbo codec of modern standards.     ·         Offers readers a complete introduction to practical turbo decoder design; ·         Describes different design methodologies and explains the trade-offs between performance improvement and overhead; ·         Explains modern techniques for state-of-the-art designs; ·         Includes simulation and implementation results with respect to various decoder circuit designs; ·         Reveals novel approaches to higher operating efficiency of turbo decoders for beyond 4G applications.Wireless communication systemsSignal processingDigital techniquesLong-Term Evolution (Telecommunications)Wireless communication systems.Signal processingDigital techniques.Long-Term Evolution (Telecommunications)004.1620621.3815621.382Wong Cheng-Chiauthttp://id.loc.gov/vocabulary/relators/aut871860Chang Hsie-ChiaMiFhGGMiFhGGBOOK9910299487803321Turbo Decoder Architecture for Beyond-4G Applications1946419UNINA