03687nam 22005295 450 991025433520332120200703001642.03-319-54714-310.1007/978-3-319-54714-5(CKB)3710000001118046(DE-He213)978-3-319-54714-5(MiAaPQ)EBC4826524(PPN)199770263(EXLCZ)99371000000111804620170320d2017 u| 0engurnn|008mamaatxtrdacontentcrdamediacrrdacarrierTesting of Interposer-Based 2.5D Integrated Circuits /by Ran Wang, Krishnendu Chakrabarty1st ed. 2017.Cham :Springer International Publishing :Imprint: Springer,2017.1 online resource (XIV, 182 p. 118 illus., 102 illus. in color.) 3-319-54713-5 Includes bibliographical references at the end of each chapters.Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-.This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.Electronic circuitsMicroprocessorsLogic designCircuits and Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/T24068Processor Architectureshttps://scigraph.springernature.com/ontologies/product-market-codes/I13014Logic Designhttps://scigraph.springernature.com/ontologies/product-market-codes/I12050Electronic circuits.Microprocessors.Logic design.Circuits and Systems.Processor Architectures.Logic Design.621.3815Wang Ranauthttp://id.loc.gov/vocabulary/relators/aut968451Chakrabarty Krishnenduauthttp://id.loc.gov/vocabulary/relators/autBOOK9910254335203321Testing of Interposer-Based 2.5D Integrated Circuits2199628UNINA