04181nam 22006855 450 991025418270332120200704015316.03-319-22035-710.1007/978-3-319-22035-2(CKB)3710000000467434(EBL)4178452(SSID)ssj0001546797(PQKBManifestationID)16141534(PQKBTitleCode)TC0001546797(PQKBWorkID)14796161(PQKB)10125591(DE-He213)978-3-319-22035-2(MiAaPQ)EBC4178452(PPN)188461655(EXLCZ)99371000000046743420150827d2016 u| 0engur|n|---|||||txtccrIP Cores Design from Specifications to Production Modeling, Verification, Optimization, and Protection /by Khaled Salah Mohamed1st ed. 2016.Cham :Springer International Publishing :Imprint: Springer,2016.1 online resource (162 p.)Analog Circuits and Signal Processing,1872-082XDescription based upon print version of record.3-319-22034-9 Includes bibliographical references at the end of each chapters.1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions.This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies. ·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; ·         Introduce a deep introduction for Verilog for both implementation and verification point of view.  ·         Demonstrates how to use IP in applications such as memory controllers and SoC buses. ·         Describes a new verification methodology called bug localization; ·         Presents a novel scan-chain methodology for RTL debugging; ·         Enables readers to employ UVM methodology in straightforward, practical terms.Analog Circuits and Signal Processing,1872-082XElectronic circuitsMicroprocessorsElectronicsMicroelectronicsCircuits and Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/T24068Processor Architectureshttps://scigraph.springernature.com/ontologies/product-market-codes/I13014Electronics and Microelectronics, Instrumentationhttps://scigraph.springernature.com/ontologies/product-market-codes/T24027Electronic circuits.Microprocessors.Electronics.Microelectronics.Circuits and Systems.Processor Architectures.Electronics and Microelectronics, Instrumentation.620Mohamed Khaled Salahauthttp://id.loc.gov/vocabulary/relators/aut761899MiAaPQMiAaPQMiAaPQBOOK9910254182703321IP Cores Design from Specifications to Production1543042UNINA