01433nam 2200481 450 991015579660332120230725063943.03-7831-8160-7(CKB)3790000000019764(EBL)2050477(OCoLC)909146246(MiAaPQ)EBC2050477(EXLCZ)99379000000001976420171215h20102010 uy 0gerur|n|---|||||rdacontentrdamediardacarrierDa sein - nah sein Wie wir unseren alten Eltern guttun können /Gertrud TeusenFreiburg im Breisgau, [Germany] :Kreuz,2010.©20101 online resource (236 p.)Description based upon print version of record.3-7831-3490-0 Includes bibliographical references.Aging parentsCareAging parentsFamily relationshipsAging parentsPsychologyAging parentsAging parentsCare.Aging parentsFamily relationships.Aging parentsPsychology.Aging parents.649.8084/6Teusen Gertrud1371290MiAaPQMiAaPQMiAaPQBOOK9910155796603321Da sein - nah sein3400226UNINA03040oam 2200481 450 991029949280332120190911112725.03-319-02378-010.1007/978-3-319-02378-6(OCoLC)867640163(MiFhGG)GVRL6VOU(EXLCZ)99371000000007462320131112d2014 uy 0engurun|---uuuuatxtccrDesign-for-test and test optimization techniques for TSV-based 3D stacked ICs /Brandon Noia, Krishnendu Chakrabarty ; foreword by Vishwani Agrawal1st ed. 2014.Cham, Switzerland :Springer,2014.1 online resource (xviii, 245 pages) illustrations (chiefly color)Gale eBooksDescription based upon print version of record.3-319-02377-2 Includes bibliographical references.Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions.This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain.  Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization.  Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.   • Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; • Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; • Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  .Three-dimensional integrated circuitsThree-dimensional integrated circuits.004.1537.622620621.3815Noia Brandonauthttp://id.loc.gov/vocabulary/relators/aut882555Chakrabarty KrishnenduAgrawal Vishwani D.1943-MiFhGGMiFhGGBOOK9910299492803321Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs1971430UNINA