04659nas0-22006491i-450-99000015921020331620090716134710.00374-35350015921USA010015921(ALEPH)000015921USA01001592119960311a----9999km-y0itay0103----baengNEafa----0--1Journal of elasticityDordrechtKluwer Academic Publ.v.ill.Comincia nel 1971Pubbl. 3 voll. di 4 fasc. l'annoTecnologia dei materialiPeriodici620.112Sistema bibliotecario di Ateneo dell' Università di SalernoRICAhttp://www.springerlink.com/content/102932/?p=9bf84b9ebf89443ebb7c006dcf2f0843&pi=0.Online da workstation autorizzate990000159210203316TECFondo1979-1990;1993-2008;1988;2007;SE1996031120001110USA011712JOHNNY9020020306USA011156PATTY9020020318USA01114220020403USA011623PATRY9020040406USA011612VITTORIANA9020090716USA011347Journal of elasticity793793UNISAUSA50AdministrativeISSUETECTECCiv F15921-10020030415200162309NON PrestabileVol.62, n. 3 (2001)200103102001031720030818USA50AdministrativeISSUETECTECCiv F15921-11020030415200163109NON PrestabileVol.63, n. 1 (2001)200104102001041720030909USA50AdministrativeISSUETECTECCiv F15921-12020030415200163209NON PrestabileVol.63, n. 2 (2001)200105102001051720030909USA50AdministrativeISSUETECTECCiv F15921-13020030415200163309NON PrestabileVol.63, n. 3 (2001)200106102001061720030909USA50AdministrativeISSUETECTECCiv F15921-14020030415200164109NON PrestabileVol.64, n. 1 (2001)200107102001071720030909USA50AdministrativeISSUETECTECCiv F15921-16020030415200164309NON PrestabileVol.64, n. 2-3 (2001)200109102001091720030909USA50AdministrativeISSUETECTECCiv F15921-19020030708200267309NON PrestabileVol.67, n. 3 (2002)200206102002061720030909USA50AdministrativeISSUETECTECCiv F15921-2020030415200266109NON PrestabileVol.66, n. 1 (2002)200201102002011720030415USA50AdministrativeISSUETECTECCiv F15921-21020031118200268309NON PrestabileVol.68, n. 1-3 (2002)200209102002091720031118USA50AdministrativeISSUETECTECCiv F15921-23020031216200269309NON PrestabileVol.69, n. 1-3 (2002)200212102002121720031216USA50AdministrativeISSUETECTECCiv F15921-25020040112200370309NON PrestabileVol.70, n. 1-3 (2003)200303102003031720040112USA50AdministrativeISSUETECTECCiv F15921-27020040112200371309NON PrestabileVol.71, n. 1-3 (2003)200306102003061720040112USA50AdministrativeISSUETECTECCiv F15921-28020040112200372109NON PrestabileVol.72, n. 1 (2003)2003071020030717USA50AdministrativeISSUETECTECCiv F15921-3020030415200266209NON PrestabileVol.66, n. 2 (2002)200202102002021720030505USA50AdministrativeISSUETECTECCiv F15921-4020030415200266309NON PrestabileVol.66, n. 3 (2002)200203102002031720030415USA50AdministrativeISSUETECTECCiv F15921-5020030415200267109NON PrestabileVol.67, n. 1 (2002)200204102002041720030415USA50AdministrativeISSUETECTECCiv F15921-6020030415200267209NON PrestabileVol.67, n. 2 (2002)200205102002051720030708USA50AdministrativeISSUETECTECCiv F15921-7020030415200165309NON PrestabileVol.65, n. 1-3 (2001)200112102001121720030909USA50AdministrativeISSUETECTECCiv F15921-8020030415200162109NON PrestabileVol.62, n. 1 (2001)200101102001011720030909USA50AdministrativeISSUETECTECCiv F15921-9020030415200162209NON PrestabileVol.62, n. 2 (2001)20010210200102172003090902482oam 2200601zu 450 991014606560332120210731015514.01-280-55652-897866105565260-471-45755-80-470-35692-80-471-45756-6(CKB)1000000000019044(SSID)ssj0000312670(PQKBManifestationID)11229677(PQKBTitleCode)TC0000312670(PQKBWorkID)10332405(PQKB)11500319(CaSebORM)9780471429760(MiAaPQ)EBC4957239(Au-PeEL)EBL4957239(CaONFJC)MIL55652(OCoLC)1024270416(EXLCZ)99100000000001904420160829d2003 uy engurunu|||||txtccrVerilog Coding for Logic Synthesis1st edition[Place of publication not identified]Wiley Interscience Imprint20031 online resource (1 v.) illBibliographic Level Mode of Issuance: Monograph0-471-42976-7 Includes bibliographical references and index.Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface.Provides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI coursesDigital electronicsLogic circuitsComputer-aided designVerilog (Computer hardware description language)Electronic books.Digital electronics.Logic circuitsComputer-aided design.Verilog (Computer hardware description language)621.395Lee Weng Fook867193PQKBBOOK9910146065603321Verilog Coding for Logic Synthesis2068017UNINA