05598nam 2200685 a 450 991014556370332120200520144314.01-281-31822-197866113182220-470-51714-X0-470-51713-1(CKB)1000000000409912(EBL)351481(SSID)ssj0000254726(PQKBManifestationID)11207026(PQKBTitleCode)TC0000254726(PQKBWorkID)10211821(PQKB)11726648(Au-PeEL)EBL351481(CaPaEBR)ebr10232603(CaONFJC)MIL131822(OCoLC)214282081(CaSebORM)9780470510827(MiAaPQ)EBC351481(EXLCZ)99100000000040991220071026d2007 uy 0engur|n|---|||||txtccrSynchronization and arbitration in digital systems[electronic resource] /David Kinniment1st editionHoboken, NJ J. Wiley & Sons20071 online resource (282 p.)Description based upon print version of record.0-470-51082-X Includes bibliographical references and index.Synchronization and Arbitration in Digital Systems; Contents; Preface; List of Contributors; Acknowledgements; 1 Synchronization, Arbitration and Choice; 1.1 INTRODUCTION; 1.2 THE PROBLEM OF CHOICE; 1.3 CHOICE IN ELECTRONICS; 1.4 ARBITRATION; 1.5 CONTINUOUS AND DISCRETE QUANTITIES; 1.6 TIMING; 1.7 BOOK STRUCTURE; Part I; 2 Modelling Metastability; 2.1 THE SYNCHRONIZER; 2.2 LATCH MODEL; 2.3 FAILURE RATES; 2.3.1 Event Histograms and MTBF; 2.4 LATCHES AND FLIP-FLOPS; 2.5 CLOCK BACK EDGE; 3 Circuits; 3.1 LATCHES AND METASTABILITY FILTERS; 3.2 EFFECTS OF FILTERING; 3.3 THE JAMB LATCH3.3.1 Jamb Latch Flip-. op3.4 LOW COUPLING LATCH; 3.5 THE Q-FLOP; 3.6 THE MUTEX; 3.7 ROBUST SYNCHRONIZER; 3.8 THE TRI-FLOP; 4 Noise and its Effects; 4.1 NOISE; 4.2 EFFECT OF NOISE ON A SYNCHRONIZER; 4.3 MALICIOUS INPUTS; 4.3.1 Synchronous Systems; 4.3.2 Asynchronous Systems; 5 Metastability Measurements; 5.1 CIRCUIT SIMULATION; 5.1.1 Time Step Control; 5.1.2 Long-term τ; 5.1.3 Using Bisection; 5.2 SYNCHRONIZER FLIP-FLOP TESTING; 5.3 RISING AND FALLING EDGES; 5.4 DELAY-BASED MEASUREMENT; 5.5 DEEP METASTABILITY; 5.6 BACK EDGE MEASUREMENT; 5.7 MEASURE AND SELECT; 5.7.1 Failure Measurement5.7.2 Synchronizer Selection6 Conclusions Part I; Part II; 7 Synchronizers in Systems; 7.1 LATENCY AND THROUGHPUT; 7.2 FIFO SYNCHRONIZER; 7.3 AVOIDING SYNCHRONIZATION; 7.4 PREDICTIVE SYNCHRONIZERS; 7.5 OTHER LOW-LATENCY SYNCHRONIZERS; 7.5.1 Locally Delayed Latching (LDL); 7.5.2 Speculative Synchronization; 7.5.2.1 Synchronization error detection; 7.5.2.2 Pipelining; 7.5.2.3 Recovery; 7.6 ASYNCHRONOUS COMMUNICATION MECHANISMS (ACM); 7.6.1 Slot Mechanisms; 7.6.2 Three-slot Mechanism; 7.6.3 Four-slot Mechanism; 7.6.4 Hardware Design and Metastability; 7.7 SOME COMMON SYNCHRONIZER DESIGN ISSUES7.7.1 Unsynchronized Paths7.7.1.1 No acknowledge; 7.7.1.2 Unsynchronized reset back edge; 7.7.2 Moving Metastability Out of Sight; 7.7.2.1 Disturbing a metastable latch; 7.7.2.2 The second chance; 7.7.2.3 Metastability blocker; 7.7.3 Multiple Synchronizer Flops; 7.7.3.1 The data synchronizer; 7.7.3.2 The redundant synchronizer; 8 Networks and Interconnects; 8.1 COMMUNICATION ON CHIP; 8.1.1 Comparison of Network Architectures; 8.2 INTERCONNECT LINKS; 8.3 SERIAL LINKS; 8.3.1 Using One Line; 8.3.2 Using Two Lines; 8.4 DIFFERENTIAL SIGNALLING; 8.5 PARALLEL LINKS; 8.5.1 One Hot Codes8.5.2 Transition Signalling8.5.3 n of m Codes; 8.5.4 Phase Encoding; 8.5.4.1 Phase encoding sender; 8.5.4.2 Receiver; 8.5.5 Time Encoding; 8.6 PARALLEL SERIAL LINKS; 9 Pausible and Stoppable Clocks in GALS; 9.1 GALS CLOCK GENERATORS; 9.2 CLOCK TREE DELAYS; 9.3 A GALS WRAPPER; 10 Conclusions Part II; Part III; 11 Arbitration; 11.1 INTRODUCTION; 11.2 ARBITER DEFINITION; 11.3 ARBITER APPLICATIONS, RESOURCE ALLOCATION POLICIES AND COMMON ARCHITECTURES; 11.4 SIGNAL TRANSITION GRAPHS, OUR MAIN MODELLING LANGUAGE; 12 Simple Two-way Arbiters; 12.1 BASIC CONCEPTS AND CONVENTIONS12.1.1 Two-phase or Non-return-to-zero (NRZ) ProtocolsToday's networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first. Current developments in integrated circuit processing are leading to an increase in the numbers of independent digital processing elements in a single system. With this comes faster communications, more networks on chip, and the demand for more reliable, more complex, and higher performance syTiming circuitsDesign and constructionDigital integrated circuitsDesign and constructionSynchronizationTiming circuitsDesign and construction.Digital integrated circuitsDesign and construction.Synchronization.621.3815Kinniment D. J(David John)992889MiAaPQMiAaPQMiAaPQBOOK9910145563703321Synchronization and arbitration in digital systems2273609UNINA