03647oam 2200445zu 450 991014545690332120241212215416.097815090998251509099824(CKB)1000000000278028(SSID)ssj0000396086(PQKBManifestationID)12111761(PQKBTitleCode)TC0000396086(PQKBWorkID)10464869(PQKB)10259984(NjHacI)991000000000278028(EXLCZ)99100000000027802820160829d2005 uy engur|||||||||||txtccr2005 international conference on reconfigurable computing and FPGAS[Place of publication not identified]IEEE Computer Society20051 online resource (183 pages) illustrationsBibliographic Level Mode of Issuance: Monograph9780769524566 0769524567 Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling, -- An image comparison circuit design," -- FPGA-based customizable systolic architecture for image processing applications," -- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method," -- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform," -- A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays," -- Rapid prototyping of a self-timed ALU with FPGAs," -- FPGA implementation of a synchronous and self-timed neuroprocessor," -- On the design of two-level reconfigurable architectures," -- A secure self-reconfiguring architecture based on open-source hardware," -- Platform for intrinsic evolution of analogue neural networks," -- High quality uniform random number generation for massively parallel simulations in FPGA," -- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks," -- Quartz: a framework for correct and efficient reconfigurable design," -- Design space exploration of coarse-grain reconfigurable DSPs," -- Optimizing register binding in FPGAs using simulated annealing," -- An FPGA-based parallel sorting architecture for the Burrows Wheeler transform," -- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices," -- Applied VHDL training methodology, EDA framework and hardware implementation platform," -- FPGA implementation of DSVPWM modulator," -- A novel FPGA implementation of a welding control using a new bus architecture," -- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004," -- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3," -- VHDL core for 1024-point radix-4 FFT computation," -- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation," -- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)," -- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences," -- Hardware/software implementation of a discrete cosine transform algorithm using SystemC.Adaptive computing systemsCongressesAdaptive computing systems004Feregrino ClaudiaCumplido RenéPQKBPROCEEDING99101454569033212005 international conference on reconfigurable computing and FPGAS2364582UNINA