01985oam 2200457zu 450 991014511480332120210807003135.01-5090-8649-81-4244-1342-7(CKB)1000000000698123(SSID)ssj0000454206(PQKBManifestationID)12203037(PQKBTitleCode)TC0000454206(PQKBWorkID)10396624(PQKB)11407619(NjHacI)991000000000698123(EXLCZ)99100000000069812320160829d2007 uy engur|||||||||||txtccr2007 European Conference on Circuit Theory and Design[Place of publication not identified]I E E E20071 online resourceBibliographic Level Mode of Issuance: Monograph1-4244-1341-9 3D discrete wavelet transform (DWT) is a compute-intensive task that is usually implemented on specific architectures in many real-time medical imaging systems. In this paper, a novel area-efficient high-throughput 3D DWT architecture is proposed based on distributed arithmetic. A tap-merging technique is used to reduce the size of DA lookup tables. The proposed architectures were designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The synthesis results show the proposed architecture has a low area cost and can run up to 85 MHz, which can perform a five-level 3D wavelet analysis for seven 128 times 128 times 128 volume images per second.Electric circuitsCongressesElectric filtersCongressesElectric networksCongressesElectric circuitsElectric filtersElectric networks621.3192PQKBPROCEEDING99101451148033212007 European Conference on Circuit Theory and Design2501857UNINA