02097oam 2200433zu 450 991014089180332120241212220020.09780769542768076954276X(CKB)2670000000058819(SSID)ssj0000527485(PQKBManifestationID)12162396(PQKBTitleCode)TC0000527485(PQKBWorkID)10525668(PQKB)10060804(NjHacI)992670000000058819(EXLCZ)99267000000005881920160829d2010 uy engur|||||||||||txtccr2010 22nd International Symposium on Computer Architecture and High Performance Computing Workshops[Place of publication not identified]IEEE20101 online resourceBibliographic Level Mode of Issuance: Monograph9781424488773 142448877X Multicore architectures are an important contribution in computing technology since they are capable of providing more processing power with better cost-benefit than single-core processors. Cores execute instructions independently but share critical resources such as L2 cache memory and data channels. Clusters using multicore architectures or multiprocessors chips (MPC's) suggest a hierarchical memory environment. Parallel applications should take advantage of such memory hierarchy to achieve high performance. This paper presents a performance analysis of a synthetic application in a multicore cluster and introduces a preliminary architecture model that considers communication through both shared memory and data channels and its impact on the application performance.Computer architectureCongressesComputer architecture004.22ieeePQKBPROCEEDING99101408918033212010 22nd International Symposium on Computer Architecture and High Performance Computing Workshops2423988UNINA