01819oam 2200433zu 450 991013909060332120241212215903.097814244665041424466504(CKB)2560000000009703(SSID)ssj0000452711(PQKBManifestationID)12169545(PQKBTitleCode)TC0000452711(PQKBWorkID)10472046(PQKB)11633746(NjHacI)992560000000009703(EXLCZ)99256000000000970320160829d2010 uy engur|||||||||||txtccr2010 28th VLSI Test Symposium[Place of publication not identified]IEEE20101 online resourceBibliographic Level Mode of Issuance: Monograph9781424466498 1424466490 Low-power test aims at reduction of power-induced effects in the circuit under test in order to prevent overtesting. In contrast, noise-aware test attempts to maximize power noise to excite the chip in worst-case situations. Does low-power test potentially lead to test escapes? Will noise-aware test sort out chips which would never fail in their actual operation? What is the right approach, or the right mix of the approaches? Is the academia working on the right problems? This panel brings together experts from academia, semiconductor, EDA and IP industry.Integrated circuitsVery large scale integrationTestingCongressesIntegrated circuitsVery large scale integrationTesting621IEEE StaffPQKBPROCEEDING99101390906033212010 28th VLSI Test Symposium2512205UNINA