02348nam 2200373 450 991013590440332120231207080854.01-55937-136-610.1109/IEEESTD.1991.101070(CKB)3780000000089909(NjHacI)993780000000089909(EXLCZ)99378000000008990920231207d1991 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierIEEE Std 1005-1991 IEEE Standard Definitions and Characterization of Floating Gate Semiconductor Arrays /Institute of Electrical and Electronics EngineersNew York, NY, USA :IEEE,1991.1 online resource (41 pages)An introduction to the physics unique to this type of memory and an overview of typical array architectures are presented. The variations on the basic floating gate nonvolatile cell structure that have been used in commercially available devices are described. The various reliability considerations involved in these devices are explored. Retention and endurance failures and the interaction between endurance, retention, and standard semiconductor failure mechanisms in determining the device failure rate are covered. How to specify and perform engineering verification of retention of data stored in the arrays is described. Effects that limit the endurance of the arrays are discussed. The specification and engineering verification of endurance are described. The more common features incorporated into the arrays and methods for testing these complex products efficiently are addressed. The effects that various forms of ionizing radiation may have on floating gate arrays and approaches to test for these effects are covered. The use of floating gate cells in nonmemory applications is briefly considered.IEEE Std 1005-1991Integrated circuitsVery large scale integrationTestingSemiconductor storage devicesIntegrated circuitsVery large scale integrationTesting.Semiconductor storage devices.621.3973NjHacINjHaclDOCUMENT9910135904403321IEEE Std 1005-19913646578UNINA