01953nam 2200373 450 991013543270332120231208095019.00-7381-0989-410.1109/IEEESTD.1997.82399(CKB)3780000000092633(NjHacI)993780000000092633(EXLCZ)99378000000009263320231208d1997 uy 0engur|||||||||||txtrdacontentcrdamediacrrdacarrierIEEE Std 1076.3-1997 IEEE Standard VHDL Synthesis Packages /Institute of Electrical and Electronics EngineersNew York :IEEE,1997.1 online resource (52 pages)The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.IEEE Std 1076.3-1997Computer hardware description languagesVHDL (Computer hardware description language)Computer hardware description languages.VHDL (Computer hardware description language)621.38101135133NjHacINjHaclDOCUMENT9910135432703321IEEE Std 1076.3-19973646730UNINA