02208oam 2200445zu 450 991013080230332120241212220426.09781467320856146732085410.1109/IOLTS20173.2012(CKB)3420000000000795(SSID)ssj0000821023(PQKBManifestationID)12370491(PQKBTitleCode)TC0000821023(PQKBWorkID)10870114(PQKB)10387699(NjHacI)993420000000000795(EXLCZ)99342000000000079520160829d2012 uy engur|||||||||||txtccr2012 IEEE 18th International on-Line Testing Symposium[Place of publication not identified]IEEE20121 online resource illustrationsBibliographic Level Mode of Issuance: Monograph9781467320825 146732082X Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. SETTOFF therefore provides an increased coverage of fault tolerance with only moderate increase in overhead, hence it is suitable for building highly reliable systems at lower cost than the traditional techniques.Electronic circuit designCongressesElectronic circuit design621IEEE StaffPQKBPROCEEDING99101308023033212012 IEEE 18th International on-Line Testing Symposium2529052UNINA