01037nam0-2200313---450-99000980774040332120140110120306.0978-88-6345-502-1000980774FED01000980774(Aleph)000980774FED0100098077420140110d2013----km-y0itay50------baitaITa-------001yy<<La >>guida del Sole 24 Ore al Project managementlo standard internazionale di PM per gestire l'innovazione nei prodotti e nei servizi, le commesse, i progetti di miglioramentoStefano Tonchia e Fabio NoninoNuova ed. aggiornataMilanoGruppo24ore2013X, 500 p.ill.24 cmTonchia,Stefano141785Nonino,Fabio329202ITUNINARICAUNIMARCBK990009807740403321AZEGI212A21382DECBCDECBCGuida del Sole 24 Ore al Project management838073UNINA01020cam0 22002531 450 SOBE0005248520160607090550.020160531d1975 |||||ita|0103 baitaITMalattie magiche di origine diabolica e loro terapia secondo il medico beneventano Pietro Piperno (✝ 1642)Michele MieleNapoliEdizioni Dehoniane1975166-223 p.24 cmEstratto da: Campania Sacra, n. 6 (1975)Miele, MicheleAF00007212070164683ITUNISOB20160607RICAUNISOBUNISOBFondo|Casavola|Opusc148194SOBE00052485M 102 Monografia moderna SBNMFondo|Casavola|Opusc000084SI148194CasavoladonoNmenleUNISOBUNISOB20160531160328.020160531160356.0menleMalattie magiche di origine diabolica e loro terapia secondo il medico beneventano Pietro Piperno (✝ 1642)1724868UNISOB09997nam 22009255 450 99646599570331620230406054950.03-540-74442-810.1007/978-3-540-74442-9(CKB)1000000000490694(SSID)ssj0000318340(PQKBManifestationID)11266632(PQKBTitleCode)TC0000318340(PQKBWorkID)10310235(PQKB)10225325(DE-He213)978-3-540-74442-9(MiAaPQ)EBC3063424(MiAaPQ)EBC337392(MiAaPQ)EBC6699191(Au-PeEL)EBL337392(CaONFJC)MIL135360(OCoLC)808680889(Au-PeEL)EBL6699191(PPN)123164451(EXLCZ)99100000000049069420100301d2007 u| 0engurnn|008mamaatxtccrIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation[electronic resource] 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings /edited by Nadine Azemard, Lars Svensson1st ed. 2007.Berlin, Heidelberg :Springer Berlin Heidelberg :Imprint: Springer,2007.1 online resource (XIV, 586 p.) Theoretical Computer Science and General Issues,2512-2029 ;4644Includes index.3-540-74441-X Includes bibliographical references and index.Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters.th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.Theoretical Computer Science and General Issues,2512-2029 ;4644Logic designMicroprocessorsComputer architectureElectronic digital computers—EvaluationComputer arithmetic and logic unitsComputer storage devicesMemory management (Computer science)Electronic circuitsLogic DesignProcessor ArchitecturesSystem Performance and EvaluationArithmetic and Logic StructuresComputer Memory StructureElectronic Circuits and SystemsLogic design.Microprocessors.Computer architecture.Electronic digital computers—Evaluation.Computer arithmetic and logic units.Computer storage devices.Memory management (Computer science).Electronic circuits.Logic Design.Processor Architectures.System Performance and Evaluation.Arithmetic and Logic Structures.Computer Memory Structure.Electronic Circuits and Systems.621.395Azemard Nadine1963-Svensson Lars1960-MiAaPQMiAaPQMiAaPQBOOK996465995703316Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation772134UNISA02014oam 2200529 a 450 991069715500332120230902162203.0(CKB)5470000002385362(OCoLC)708356590(EXLCZ)99547000000238536220110324d2010 ua 0engurmn|||||||||txtrdacontentcrdamediacrrdacarrierUnited States airline transport pilot international flight language experiences[electronic resource]Report 2Word meaning and pronunciation /O. Veronika Prinzo ... [and others]Washington, D.C. :Federal Aviation Administration, Office of Aerospace Medicine,[2010]1 online resource (ix, 36 pages) illustrations"April 2010."Title from title screen (viewed on Mar. 24, 2011)."DOT/FAA/AM-10/7."Includes bibliographical references.Word meaning and pronunciationAir pilotsUnited StatesLanguageAir traffic controllersLanguageListening comprehensionUnited StatesEnglish languagePronunciationAir pilotsUnited StatesPsychologyAeronauticsCommunication systemsAeronauticsSafety measuresAir pilotsLanguage.Air traffic controllersLanguage.Listening comprehensionEnglish languagePronunciation.Air pilotsPsychology.AeronauticsCommunication systems.AeronauticsSafety measures.Prinzo O. Veronika1381114United States.Office of Aerospace Medicine.GPOGPOGPOBOOK9910697155003321United States airline transport pilot international flight language experiences3492665UNINA