00990nam0-2200337---450-99000943000040332120110922123753.0978-88-430-4934-9000943000FED01000943000(Aleph)000943000FED0100094300020110922d2009----km-y0itay50------baitaITa-------101yyLabirinti di Psicheinterpretazioni e variazioni sul mitoa cura di Anna Maria PedullàRomaCarocci2009151 p.22 ill.22 cmLingue e letterature Carocci98Amore e PsicheMitiCongressi2007Miti nella letteratura809.933 51Pedullà,Anna MariaITUNINAREICATUNIMARCBK990009430000403321809.93351 PED 1Dip.f.m.18345FLFBCFLFBCLabirinti di Psiche760340UNINA05934nam 2200829Ia 450 991080834630332120200520144314.0978661328288097812832828881283282887978111814653811181465309781118146521111814652297811181465071118146506(CKB)2670000000128082(EBL)817361(OCoLC)757486963(SSID)ssj0000554671(PQKBManifestationID)11308402(PQKBTitleCode)TC0000554671(PQKBWorkID)10516823(PQKB)10946358(MiAaPQ)EBC817361(Au-PeEL)EBL817361(CaPaEBR)ebr10560671(CaONFJC)MIL328288(PPN)179237667(Perlego)2758610(EXLCZ)99267000000012808220110527d2011 uy 0engur|n|---|||||txtccrEmbedded SOPC design with NIOS II processor and VHDL examples /Pong P. Chu1st ed.Hoboken, N.J. Wileyc20111 online resource (738 p.)Description based upon print version of record.9781118008881 111800888X Includes bibliographical references and index.Embedded SOPC Design with Nios II Processor and VHDL Examples; CONTENTS; Preface; Acknowledgments; 1 Overview of Embedded System; 1.1 Introduction; 1.1.1 Definition of an embedded system; 1.1.2 Example systems; 1.2 System design requirements; 1.3 Embedded SoPC systems; 1.3.1 Basic development flow; 1.4 Book organization; 1.5 Bibliographic notes; PART I BASIC DIGITAL CIRCUITS DEVELOPMENT; 2 Gate-level Combinational Circuit; 2.1 Overview of VHDL; 2.2 General description; 2.2.1 Basic lexical rules; 2.2.2 Library and package; 2.2.3 Entity declaration; 2.2.4 Data type and operators2.2.5 Architecture body2.2.6 Code of a 2-bit comparator; 2.3 Structural description; 2.4 Testbench; 2.5 Bibliographic notes; 2.6 Suggested experiments; 2.6.1 Code for gate-level greater-than circuit; 2.6.2 Code for gate-level binary decoder; 3 Overview of FPGA and EDA Software; 3.1 FPGA; 3.1.1 Overview of a general FPGA device; 3.1.2 Overview of the Altera Cyclone II devices; 3.2 Overview of the Altera DE1 and DE2 boards; 3.3 Development flow; 3.4 Overview of Quartus II; 3.5 Short tutorial of Quartus II; 3.5.1 Create the design project; 3.5.2 Create a testbench and perform the RTL simulation3.5.3 Compile the project3.5.4 Perform timing analysis; 3.5.5 Program the FPGA device; 3.6 Short tutorial on the ModelSim HDL simulator; 3.7 Bibliographic notes; 3.8 Suggested experiments; 3.8.1 Gate-level greater-than circuit; 3.8.2 Gate-level binary decoder; 4 RT-level Combinational Circuit; 4.1 RT-level components; 4.1.1 Relational operators; 4.1.2 Arithmetic operators; 4.1.3 Other synthesis-related VHDL constructs; 4.1.4 Summary; 4.2 Routing circuit with concurrent assignment statements; 4.2.1 Conditional signal assignment statement; 4.2.2 Selected signal assignment statement4.3 Modeling with a process4.3.1 Process; 4.3.2 Sequential signal assignment statement; 4.4 Routing circuit with if and case statements; 4.4.1 If statement; 4.4.2 Case statement; 4.4.3 Comparison to concurrent statements; 4.4.4 Unintended memory; 4.5 Constants and generics; 4.5.1 Constants; 4.5.2 Generics; 4.6 Design examples; 4.6.1 Hexadecimal digit to seven-segment LED decoder; 4.6.2 Sign-magnitude adder; 4.6.3 Barrel shifter; 4.6.4 Simplified floating-point adder; 4.7 Bibliographic notes; 4.8 Suggested experiments; 4.8.1 Multi-function barrel shifter; 4.8.2 Dual-priority encoder4.8.3 BCD incrementor4.8.4 Floating-point greater-than circuit; 4.8.5 Floating-point and signed integer conversion circuit; 4.8.6 Enhanced floating-point adder; 5 Regular Sequential Circuit; 5.1 Introduction; 5.1.1 D FF and register; 5.1.2 Synchronous system; 5.1.3 Code development; 5.2 HDL code of the basic storage elements; 5.2.1 D FF; 5.2.2 Register; 5.2.3 Register file; 5.2.4 SRAM; 5.3 Simple design examples; 5.3.1 Shift register; 5.3.2 Binary counter and variant; 5.4 Testbench for sequential circuits; 5.5 Timing analysis; 5.5.1 Timing parameters; 5.5.2 Timing considerations in Quartus II5.6 Case studyThe book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a MandelbSystems on a chipField programmable gate arraysComputer input-output equipmentDesign and constructionVHDL (Computer hardware description language)Systems on a chip.Field programmable gate arrays.Computer input-output equipmentDesign and construction.VHDL (Computer hardware description language)621.392621.392621.395TEC008010bisacshChu Pong P.1959-521922MiAaPQMiAaPQMiAaPQBOOK9910808346303321Embedded SOPC design with NIOS II processor and VHDL examples4028575UNINA