02430nlm0 22006371i 450 9900092591704033219783540959489000925917FED01000925917(Aleph)000925917FED0100092591720100926d2009----km-y0itay50------baengDEdrnn-008mamaaIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and SimulationRisorsa elettronica18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papersedited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, Lars Svensson, José MonteiroBerlin ; HeidelbergSpringer2009Lecture Notes in Computer Science0302-97435349Documento elettronicoTestoFormato html, pdfHutchison,DavidKanade,TakeoKittler,JosefKleinberg,Jon M.Mattern,FriedemannMitchell,John C.Monteiro,JoséNaor,MoniNierstrasz,OscarPandu Rangan,C.Steffen,BernhardSudan,MadhuSvensson,LarsTerzopoulos,DemetriTygar,DougVardi,Moshe Y.Weikum,GerhardITUNINAREICATUNIMARCFull text per gli utenti Federico IIhttp://dx.doi.org/10.1007/978-3-540-95948-9EB990009259170403321Arithmetic and Logic StructuresCircuits and SystemsComputer scienceComputer ScienceComputer system performanceLogic designLogic DesignMemory management (Computer science)Memory StructuresProcessor ArchitecturesSystem Performance and EvaluationSystems engineeringIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation772134UNINA